| V1 |
|
87.50% |
| V2 |
|
20.69% |
| V2S |
|
37.50% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| kmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| kmac_csr_hw_reset | 0.440s | 23.444us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| kmac_csr_rw | 0.540s | 105.928us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| kmac_csr_bit_bash | 5.980s | 3107.210us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| kmac_csr_aliasing | 0.890s | 75.435us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 1.090s | 80.644us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| kmac_csr_rw | 0.540s | 105.928us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 0.890s | 75.435us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| kmac_mem_walk | 0.380s | 16.750us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| kmac_mem_partial_access | 0.640s | 65.463us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 0 | 1 | 0.00 | |||
| kmac_long_msg_and_output | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| burst_write | 0 | 1 | 0.00 | |||
| kmac_burst_write | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| test_vectors | 0 | 8 | 0.00 | |||
| kmac_test_vectors_sha3_224 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_sha3_256 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_sha3_384 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_sha3_512 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_shake_128 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_shake_256 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_kmac | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_test_vectors_kmac_xof | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sideload | 0 | 1 | 0.00 | |||
| kmac_sideload | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| app | 0 | 1 | 0.00 | |||
| kmac_app | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| app_with_partial_data | 0 | 1 | 0.00 | |||
| kmac_app_with_partial_data | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_refresh | 0 | 1 | 0.00 | |||
| kmac_entropy_refresh | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| error | 0 | 1 | 0.00 | |||
| kmac_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| key_error | 0 | 1 | 0.00 | |||
| kmac_key_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sideload_invalid | 0 | 1 | 0.00 | |||
| kmac_sideload_invalid | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_timeout_error | 0 | 1 | 0.00 | |||
| kmac_edn_timeout_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_mode_error | 0 | 1 | 0.00 | |||
| kmac_entropy_mode_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| entropy_ready_error | 0 | 1 | 0.00 | |||
| kmac_entropy_ready_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_escalation | 0 | 1 | 0.00 | |||
| kmac_lc_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| kmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| kmac_intr_test | 0.420s | 41.864us | 1 | 1 | 100.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| kmac_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 1.720s | 220.170us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 1.720s | 220.170us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 0.440s | 23.444us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 0.540s | 105.928us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 0.890s | 75.435us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 0.800s | 57.476us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 0.440s | 23.444us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 0.540s | 105.928us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 0.890s | 75.435us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 0.800s | 57.476us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 0.960s | 102.563us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 0.960s | 102.563us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 0.960s | 102.563us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 0.960s | 102.563us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 1.050s | 210.940us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| kmac_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_tl_intg_err | 1.810s | 329.107us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| kmac_tl_intg_err | 1.810s | 329.107us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 0 | 1 | 0.00 | |||
| kmac_lc_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_sw_key_key_masking | 0 | 1 | 0.00 | |||
| kmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_sideload | 0 | 1 | 0.00 | |||
| kmac_sideload | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cfg_shadowed_config_shadow | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 0.960s | 102.563us | 1 | 1 | 100.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| kmac_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| kmac_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_packer_ctr_redun | 0 | 1 | 0.00 | |||
| kmac_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cfg_shadowed_config_regwen | 0 | 1 | 0.00 | |||
| kmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_global_esc | 0 | 1 | 0.00 | |||
| kmac_lc_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_local_esc | 0 | 1 | 0.00 | |||
| kmac_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_absorbed_ctrl_mubi | 0 | 1 | 0.00 | |||
| kmac_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 0 | 1 | 0.00 | |||
| kmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 27 test runs | |||
| kmac_smoke | 31232856113713370777789976077575666521137892620512270434950694135715292469818 | None | ||
| kmac_long_msg_and_output | 93768856158963650726604423194644694548838355357610441415885298632938138884678 | None | ||
| kmac_sideload | 19632282446404121576626721769819085682645112898670770642439246075695061189207 | None | ||
| kmac_sideload_invalid | 15963024213283947871687180181903349415005758334946473096142020705330778527279 | None | ||
| kmac_burst_write | 96822561013973224450221931168425341869133081024969780556223671806443296007744 | None | ||
| kmac_test_vectors_sha3_224 | 33345081254092227566033886410370772795664596429646692383173111512542942864849 | None | ||
| kmac_test_vectors_sha3_256 | 104880952271624753318010030660595361219162172084481513910155815662334141443410 | None | ||
| kmac_test_vectors_sha3_384 | 88792821160943912639758555038453268653233335699917317096085197223155842836132 | None | ||
| kmac_test_vectors_sha3_512 | 22375691556025529075511363928161619687966014139244202800958559187839777547295 | None | ||
| kmac_test_vectors_shake_128 | 103122693832999795724730075798612439548348045633392658898842942672268578887539 | None | ||
| kmac_test_vectors_shake_256 | 20429231905312866889740844269328162834617846283060540215014721133262510427368 | None | ||
| kmac_test_vectors_kmac | 70615506984355915842883188377706186923597918902518785689574147151440932512807 | None | ||
| kmac_test_vectors_kmac_xof | 86253428740967926326370870782153456803666637009843754365423042159151036599907 | None | ||
| kmac_app | 106923984879286862241453050627313087769815530228328283768814005022913914579501 | None | ||
| kmac_app_with_partial_data | 58734897924650359638039207098817845213617719608097329592415622800782760075081 | None | ||
| kmac_entropy_refresh | 21359074311812824225848829907379771667463737894538975805380482377521518193302 | None | ||
| kmac_mubi | 13538233158942728053013756321709264940738021043299139912579433707950687451160 | None | ||
| kmac_error | 31011204193037145721769231365539827322249471415274881753557701379730113209899 | None | ||
| kmac_key_error | 36403755015778296880349261001844763439693827227279002940636618054653245439031 | None | ||
| kmac_edn_timeout_error | 10097351975209752212043365511357852968375600955783150788781755858690336996168 | None | ||
| kmac_entropy_mode_error | 67692491633053803130697542748275712803124785778478155802799513157415293781071 | None | ||
| kmac_entropy_ready_error | 97211759930144421025784369035144862532386907430442645586708905346412859259946 | None | ||
| kmac_lc_escalation | 44941260485101100409117209230984294989361692898560118986260253483482351155858 | None | ||
| kmac_stress_all | 58365710785109250385951761559893711077304952448908558155329749492227311752692 | None | ||
| kmac_stress_all_with_rand_reset | 26755810084160417319769108319853232905149704867687568709475271409403398459909 | None | ||
| kmac_sec_cm | 89461103632070326682391027426195343529220698799562669490335618330155340810541 | None | ||
| kmac_alert_test | 56509996722760507201961890055101602480480718368653187071708959798721662249694 | None | ||
| Job returned a non-zero exit code: * | 1 test run | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.089 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
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