Simulation Results: lc_ctrl/volatile_unlock_disabled

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.47 %
  • code
  • 83.76 %
  • assert
  • 94.83 %
  • func
  • 92.83 %
  • line
  • 97.15 %
  • branch
  • 93.61 %
  • cond
  • 79.17 %
  • toggle
  • 85.31 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
93.33%
V2S
90.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.500s 50.114us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.450s 23.816us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.410s 28.569us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.760s 249.265us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.460s 28.758us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.530s 57.757us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.410s 28.569us 1 1 100.00
lc_ctrl_csr_aliasing 0.460s 28.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.280s 354.801us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 2.080s 893.081us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.410s 16.781us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 0.650s 25.898us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 2.730s 4381.756us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_prog_failure 0.650s 25.898us 1 1 100.00
lc_ctrl_errors 2.730s 4381.756us 1 1 100.00
lc_ctrl_security_escalation 2.790s 1198.109us 1 1 100.00
lc_ctrl_jtag_state_failure 19.170s 14683.401us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.900s 371.366us 1 1 100.00
lc_ctrl_jtag_errors 15.040s 2742.218us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 1.520s 952.043us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.650s 3280.010us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.900s 371.366us 1 1 100.00
lc_ctrl_jtag_errors 15.040s 2742.218us 1 1 100.00
lc_ctrl_jtag_access 2.010s 337.718us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 3.590s 1187.393us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 0.860s 281.253us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.710s 160.954us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 2.140s 3843.473us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 0.800s 1026.603us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.500s 17.598us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.310s 203.384us 1 1 100.00
lc_ctrl_jtag_alert_test 0.440s 24.843us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.430s 757.821us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.520s 16.470us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 41.120s 6053.616us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.460s 213.747us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.330s 347.110us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.330s 347.110us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.450s 23.816us 1 1 100.00
lc_ctrl_csr_rw 0.410s 28.569us 1 1 100.00
lc_ctrl_csr_aliasing 0.460s 28.758us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.730s 49.597us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.450s 23.816us 1 1 100.00
lc_ctrl_csr_rw 0.410s 28.569us 1 1 100.00
lc_ctrl_csr_aliasing 0.460s 28.758us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.730s 49.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
lc_ctrl_tl_intg_err 0.790s 71.730us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 0.790s 71.730us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 2.080s 893.081us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.950s 4601.901us 1 1 100.00
lc_ctrl_sec_cm 3.880s 435.562us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 2.790s 1198.109us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 2.280s 354.801us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.650s 3280.010us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.110s 1838.298us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.110s 1838.298us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 2.900s 579.012us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.170s 279.595us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.170s 279.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.110s 968.720us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_post_trans 89469085227124878805892432032940216797685344731143301670849843346628869443419 472
UVM_INFO @ 3280009534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 46559428632623934081518953512729579114541250402341009181909240777734874353414 7139
UVM_INFO @ 6053615888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 106778229633493082692952250667967401686229623791838513722833291581962067377964 177
UVM_INFO @ 968719825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---