Simulation Results: lc_ctrl/volatile_unlock_enabled

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.26 %
  • code
  • 83.29 %
  • assert
  • 94.13 %
  • func
  • 93.37 %
  • line
  • 97.00 %
  • branch
  • 93.00 %
  • cond
  • 79.28 %
  • toggle
  • 83.64 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.530s 14.414us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.440s 48.172us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.420s 101.349us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.710s 109.756us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.480s 69.997us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.520s 108.024us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.420s 101.349us 1 1 100.00
lc_ctrl_csr_aliasing 0.480s 69.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.130s 98.970us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.580s 284.732us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.400s 21.043us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.290s 99.979us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 2.140s 1489.424us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_prog_failure 1.290s 99.979us 1 1 100.00
lc_ctrl_errors 2.140s 1489.424us 1 1 100.00
lc_ctrl_security_escalation 2.080s 961.609us 1 1 100.00
lc_ctrl_jtag_state_failure 10.610s 1246.408us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.910s 1114.484us 1 1 100.00
lc_ctrl_jtag_errors 22.540s 17738.729us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.550s 970.468us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.530s 2535.211us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.910s 1114.484us 1 1 100.00
lc_ctrl_jtag_errors 22.540s 17738.729us 1 1 100.00
lc_ctrl_jtag_access 3.160s 1230.920us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.130s 1802.504us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 0.590s 535.534us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.600s 239.162us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.550s 800.210us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 0.590s 112.238us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.610s 243.633us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 0.600s 98.503us 1 1 100.00
lc_ctrl_jtag_alert_test 0.610s 63.575us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.100s 3181.225us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.470s 16.318us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 23.010s 14812.232us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.430s 15.246us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.380s 155.046us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.380s 155.046us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.440s 48.172us 1 1 100.00
lc_ctrl_csr_rw 0.420s 101.349us 1 1 100.00
lc_ctrl_csr_aliasing 0.480s 69.997us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.500s 100.502us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.440s 48.172us 1 1 100.00
lc_ctrl_csr_rw 0.420s 101.349us 1 1 100.00
lc_ctrl_csr_aliasing 0.480s 69.997us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.500s 100.502us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
lc_ctrl_tl_intg_err 0.770s 242.795us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 0.770s 242.795us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.580s 284.732us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.840s 284.663us 1 1 100.00
lc_ctrl_sec_cm 3.980s 1120.566us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 2.080s 961.609us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.130s 98.970us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.530s 2535.211us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 2.190s 2138.723us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 2.190s 2138.723us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.670s 736.792us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.060s 359.747us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.060s 359.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 11.330s 2521.151us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_stress_all_with_rand_reset 103140399409446279510272747889071425788263175564135297535945414253805404674923 6790
UVM_INFO @ 2521151131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---