| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 0 | 1 | 0.00 | |||
| otp_ctrl_wake_up | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| smoke | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| otp_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| otp_ctrl_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| otp_ctrl_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 0 | 1 | 0.00 | |||
| otp_ctrl_partition_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| init_fail | 0 | 1 | 0.00 | |||
| otp_ctrl_init_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| partition_check | 0 | 2 | 0.00 | |||
| otp_ctrl_background_chks | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_check_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_during_otp_init | 0 | 1 | 0.00 | |||
| otp_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| partition_lock | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interface_key_check | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_key_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_interactions | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_dai_errors | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_macro_errors | 0 | 1 | 0.00 | |||
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| test_access | 0 | 1 | 0.00 | |||
| otp_ctrl_test_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| otp_ctrl_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| otp_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_secret_mem_scramble | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_digest | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_seed_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_entropy_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_integ_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_cnsty_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_lfsr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_data_reg_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_init_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_data_reg_bkgn_chk | 0 | 1 | 0.00 | |||
| otp_ctrl_check_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_regren | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_sw_unreadable | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_sw_unwritable | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_access_ctrl_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_valid_ctrl_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_test_bus_lc_gated | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_direct_access_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_check_trigger_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_check_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_macro_mem_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 0 | 1 | 0.00 | |||
| otp_ctrl_low_freq_read | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 31 test runs | |||
| otp_ctrl_wake_up | 30844465980462143021797078612758259948231317910019169000330715820378227031903 | None | ||
| otp_ctrl_smoke | 13448043218130485190502830874744328172513202158689998514434736865777258039109 | None | ||
| otp_ctrl_partition_walk | 45057885789585326590188215041698957499142937763240698936671048554977182685179 | None | ||
| otp_ctrl_low_freq_read | 74579005466617655710713951514578286850246351386195474478170566215014419622434 | None | ||
| otp_ctrl_init_fail | 72988064545103776996229748862986645436665169441913668695156284011965104107667 | None | ||
| otp_ctrl_background_chks | 99212074953464704187606801802775382829086883580602817566120949613538286067422 | None | ||
| otp_ctrl_parallel_lc_req | 12333427519316849127928374332756864169529333273878520352525964421354752339897 | None | ||
| otp_ctrl_parallel_lc_esc | 93978922902671783941591093768257548737494574337031078309173134027875165206755 | None | ||
| otp_ctrl_dai_lock | 92857124258066981294918034685793225557488131602234937741276924066904050528058 | None | ||
| otp_ctrl_dai_errs | 21812231978032678262311303933862830693208027886166712487047445166360662054705 | None | ||
| otp_ctrl_check_fail | 52557539128449296431912106121417767578664984392671680798028560006208174915653 | None | ||
| otp_ctrl_macro_errs | 59574749936044004959934469578608067359733500433795518310430696888648414878467 | None | ||
| otp_ctrl_parallel_key_req | 86213682769081753452685684152253624887590962878987538259088418018294102078947 | None | ||
| otp_ctrl_regwen | 85023590764506749605312935663535161382640416702988157893559061219961338033326 | None | ||
| otp_ctrl_test_access | 111187099192844979426723235002221352982682685347903866529151558774415713243847 | None | ||
| otp_ctrl_stress_all_with_rand_reset | 31586340726836979520753431192561352324753874376788559577152506104641941210166 | None | ||
| otp_ctrl_stress_all | 30116372631820939019842484273882678861686593542411196355943568709713041034588 | None | ||
| otp_ctrl_sec_cm | 18801095904700757042757207538356596407217829943791779500981672738548785703110 | None | ||
| otp_ctrl_tl_errors | 91305123690773542071505208673428596317473971950202650550446609097381150204311 | None | ||
| otp_ctrl_tl_intg_err | 17265161091046596280425860060993740569438149769223592835002476014312105352448 | None | ||
| otp_ctrl_alert_test | 3347612226063577108136040612521215985796104917541415097241164686305167545875 | None | ||
| otp_ctrl_intr_test | 44584880969572280640623763964550398368366779386140857043533621720569580222573 | None | ||
| otp_ctrl_mem_walk | 81291480521135304110926270351062867283440465715338859924036075064349357620412 | None | ||
| otp_ctrl_mem_partial_access | 70806628651446062452824286887777650152445191392275272668820096778306934387472 | None | ||
| otp_ctrl_csr_hw_reset | 44813093631865775219904344911379426251298970203162895026042117195038684787137 | None | ||
| otp_ctrl_csr_rw | 42261899116847702512239227323251691052985221089532744349042257860946613832321 | None | ||
| otp_ctrl_csr_bit_bash | 19476079778537431262023648169700497800605656021433069392620318791036329617521 | None | ||
| otp_ctrl_csr_aliasing | 64819082287835608001715649464236679700227416184085529267014407637834881807685 | None | ||
| otp_ctrl_same_csr_outstanding | 97901375298268855617431112593871730616791919303278060826884959094548532982047 | None | ||
| otp_ctrl_csr_mem_rw_with_rand_reset | 71615864844450924886184840806495619164174332391637674852592843680821918591619 | None | ||
| otp_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
recompiling module tb
All of 169 modules done
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 26.928 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 1
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.082 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| otp_ctrl | None | None | ||