| unmapped |
|
75.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 3 | 4 | 75.00 | |||
| prim_lfsr_fib_test | 67.726s | 0.000us | 0 | 1 | 0.00 | |
| prim_lfsr_fib_smoke | 0.520s | 1202.690us | 1 | 1 | 100.00 | |
| prim_lfsr_gal_test | 61.500s | 336715.430us | 1 | 1 | 100.00 | |
| prim_lfsr_gal_smoke | 0.590s | 1662.190us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 1 test run | |||
| prim_lfsr_fib_test | 56630588147735998930289786588265041361639431391543667038127137602585045798202 | None |
Chronologic VCS simulator copyright 1991-2025
Contains Synopsys proprietary information.
Compiler version X-2025.06-SP2-1_Full64; Runtime version X-2025.06-SP2-1_Full64; Sep 8 16:52 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
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