Simulation Results: pwrmgr

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.95 %
  • code
  • 94.42 %
  • assert
  • 97.39 %
  • func
  • 96.05 %
  • line
  • 98.93 %
  • branch
  • 95.43 %
  • cond
  • 93.92 %
  • toggle
  • 89.83 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
72.73%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.350s 24.701us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.360s 39.537us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.370s 21.323us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 0.890s 178.198us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.350s 27.737us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.570s 86.836us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.370s 21.323us 1 1 100.00
pwrmgr_csr_aliasing 0.350s 27.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.450s 548.379us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.450s 548.379us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.460s 23.406us 1 1 100.00
pwrmgr_lowpower_invalid 0.350s 72.684us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.320s 48.350us 1 1 100.00
pwrmgr_reset_invalid 0.390s 168.237us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.320s 48.350us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.620s 238.963us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.510s 385.703us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.360s 33.761us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 60.941s 0.000us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.320s 47.741us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 0.800s 63.052us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 0.800s 63.052us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.360s 39.537us 1 1 100.00
pwrmgr_csr_rw 0.370s 21.323us 1 1 100.00
pwrmgr_csr_aliasing 0.350s 27.737us 1 1 100.00
pwrmgr_same_csr_outstanding 0.370s 78.145us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.360s 39.537us 1 1 100.00
pwrmgr_csr_rw 0.370s 21.323us 1 1 100.00
pwrmgr_csr_aliasing 0.350s 27.737us 1 1 100.00
pwrmgr_same_csr_outstanding 0.370s 78.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.021s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.021s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.440s 821.533us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.620s 238.963us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.130s 747.364us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.450s 166.878us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.330s 39.632us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.025s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.330s 28.616us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.023s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.390s 140.471us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.370s 21.323us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.370s 21.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.410s 95.644us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 0.950s 10007.299us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
pwrmgr_glitch 63905737781901608502245850598054993600510489798845434222482182852400105814890 None
pwrmgr_tl_intg_err 74382219831479159609174911779726204667663481078590087380149099420039148630332 None
pwrmgr_sec_cm 21637353008985198485027903015018314802873206170096339525148959168379655113278 None
Offending '(pwr_rst_o.rst_lc_req == *'b11)' 1 test run
pwrmgr_escalation_timeout 63936041340243471066249500458015187151687429829003316220173933026569148076987 82
UVM_ERROR @ 95643594 ps: (pwrmgr.sv:178) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
UVM_INFO @ 95643594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [pwrmgr_common_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all_with_rand_reset 39649036341617174597894803137880933043224396012496455090392717109516049269789 84
UVM_INFO @ 10007298667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
pwrmgr_stress_all 94646042973951204812364135733020523819270634734837733467942440544092210112513 None
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Compiler version X-2025.06-SP2-1_Full64; Runtime version X-2025.06-SP2-1_Full64; Sep 8 16:52 2026
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make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255