Simulation Results: rom_ctrl/192kb

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 94.18 %
  • code
  • 91.55 %
  • assert
  • 97.24 %
  • func
  • 93.76 %
  • line
  • 98.95 %
  • branch
  • 98.56 %
  • cond
  • 98.22 %
  • toggle
  • 95.34 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.990s 4022.065us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.530s 68.489us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.280s 92.840us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.160s 86.881us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.200s 74.072us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.550s 121.053us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.280s 92.840us 1 1 100.00
rom_ctrl_csr_aliasing 4.200s 74.072us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.180s 74.820us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.120s 59.811us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.930s 12.303us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.260s 158.577us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.350s 3966.582us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.890s 73.949us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.190s 1049.857us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.190s 1049.857us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.530s 68.489us 1 1 100.00
rom_ctrl_csr_rw 4.280s 92.840us 1 1 100.00
rom_ctrl_csr_aliasing 4.200s 74.072us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.020s 78.496us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.530s 68.489us 1 1 100.00
rom_ctrl_csr_rw 4.280s 92.840us 1 1 100.00
rom_ctrl_csr_aliasing 4.200s 74.072us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.020s 78.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.690s 244.013us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 361.220s 744.622us 1 1 100.00
rom_ctrl_tl_intg_err 147.940s 191.182us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 361.220s 744.622us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 361.220s 744.622us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 361.220s 744.622us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 361.220s 744.622us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.990s 4022.065us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.990s 4022.065us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.990s 4022.065us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 147.940s 191.182us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
rom_ctrl_kmac_err_chk 11.350s 3966.582us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 118.020s 51491.316us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 14.690s 244.013us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 361.220s 744.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 11.060s 23500.252us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 93013857566107030865879691834683693902797896528119202164185525210545100537743 85
UVM_INFO @ 12303033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---