Simulation Results: rstmgr

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 98.11 %
  • code
  • 99.29 %
  • assert
  • 98.26 %
  • func
  • 96.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 0.720s 138.148us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.460s 131.570us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.440s 71.610us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.030s 1247.002us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.490s 106.944us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.470s 126.861us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.440s 71.610us 1 1 100.00
rstmgr_csr_aliasing 0.490s 106.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.450s 126.147us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.970s 182.541us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.900s 336.409us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.130s 1865.131us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.130s 1865.131us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.130s 1865.131us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.130s 1865.131us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 22.310s 13600.771us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.410s 71.247us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.390s 201.900us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.390s 201.900us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.460s 131.570us 1 1 100.00
rstmgr_csr_rw 0.440s 71.610us 1 1 100.00
rstmgr_csr_aliasing 0.490s 106.944us 1 1 100.00
rstmgr_same_csr_outstanding 0.810s 222.361us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.460s 131.570us 1 1 100.00
rstmgr_csr_rw 0.440s 71.610us 1 1 100.00
rstmgr_csr_aliasing 0.490s 106.944us 1 1 100.00
rstmgr_same_csr_outstanding 0.810s 222.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 13.490s 17219.168us 1 1 100.00
rstmgr_tl_intg_err 0.960s 430.109us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 13.490s 17219.168us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 13.490s 17219.168us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 0.960s 430.109us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.550s 121.871us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.250s 1412.546us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.610s 302.537us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 13.490s 17219.168us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.440s 71.610us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.440s 71.610us 1 1 100.00