Simulation Results: rv_timer

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 94.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.300s 26.271us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.300s 62.817us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.300s 14.710us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.350s 302.750us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.310s 16.283us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.460s 18.301us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.300s 14.710us 1 1 100.00
rv_timer_csr_aliasing 0.310s 16.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.730s 609.022us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 0.720s 2795.101us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 149.650s 857754.436us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 149.650s 857754.436us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.020s 5841.665us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.290s 54.597us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.290s 40.633us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.500s 70.684us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.500s 70.684us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.300s 62.817us 1 1 100.00
rv_timer_csr_rw 0.300s 14.710us 1 1 100.00
rv_timer_csr_aliasing 0.310s 16.283us 1 1 100.00
rv_timer_same_csr_outstanding 0.370s 54.730us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.300s 62.817us 1 1 100.00
rv_timer_csr_rw 0.300s 14.710us 1 1 100.00
rv_timer_csr_aliasing 0.310s 16.283us 1 1 100.00
rv_timer_same_csr_outstanding 0.370s 54.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.430s 60.148us 1 1 100.00
rv_timer_tl_intg_err 0.450s 52.688us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.450s 52.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.320s 54.564us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.310s 169.775us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 19.060s 3986.998us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 99212951427794314466549125585346007462598780738617032957744100669626628572872 81
UVM_INFO @ 54563670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 99074571623323777298602444152150291865772150082182598306945289254816690334173 81
UVM_INFO @ 169774891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---