| V1 |
|
12.50% |
| V2 |
|
70.37% |
| V2S |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 49.350s | 28105.062us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| spi_device_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| spi_device_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| spi_device_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| spi_device_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| spi_device_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| spi_device_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| spi_device_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 1 | 1 | 100.00 | |||
| spi_device_csb_read | 0.430s | 25.015us | 1 | 1 | 100.00 | |
| mem_parity | 0 | 1 | 0.00 | |||
| spi_device_mem_parity | 0.370s | 2.872us | 0 | 1 | 0.00 | |
| mem_cfg | 0 | 1 | 0.00 | |||
| spi_device_ram_cfg | 0.360s | 3.133us | 0 | 1 | 0.00 | |
| tpm_read | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 0.480s | 23.148us | 1 | 1 | 100.00 | |
| tpm_write | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 0.480s | 23.148us | 1 | 1 | 100.00 | |
| tpm_hw_reg | 2 | 2 | 100.00 | |||
| spi_device_tpm_read_hw_reg | 0.900s | 412.858us | 1 | 1 | 100.00 | |
| spi_device_tpm_sts_read | 0.420s | 205.692us | 1 | 1 | 100.00 | |
| tpm_fully_random_case | 1 | 1 | 100.00 | |||
| spi_device_tpm_all | 17.340s | 37063.106us | 1 | 1 | 100.00 | |
| pass_cmd_filtering | 2 | 2 | 100.00 | |||
| spi_device_pass_cmd_filtering | 3.040s | 1375.685us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| pass_addr_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 3.790s | 5562.355us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| pass_payload_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 3.790s | 5562.355us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| cmd_info_slots | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| cmd_read_status | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.940s | 879.004us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| cmd_read_jedec | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.940s | 879.004us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| cmd_read_sfdp | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.940s | 879.004us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| cmd_fast_read | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.940s | 879.004us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| cmd_read_pipeline | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.940s | 879.004us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| flash_cmd_upload | 1 | 1 | 100.00 | |||
| spi_device_upload | 13.880s | 11810.512us | 1 | 1 | 100.00 | |
| mailbox_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 14.400s | 3136.447us | 1 | 1 | 100.00 | |
| mailbox_cross_outside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 14.400s | 3136.447us | 1 | 1 | 100.00 | |
| mailbox_cross_inside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 14.400s | 3136.447us | 1 | 1 | 100.00 | |
| cmd_read_buffer | 2 | 2 | 100.00 | |||
| spi_device_flash_mode | 7.750s | 4693.406us | 1 | 1 | 100.00 | |
| spi_device_read_buffer_direct | 1.620s | 933.349us | 1 | 1 | 100.00 | |
| cmd_dummy_cycle | 2 | 2 | 100.00 | |||
| spi_device_mailbox | 14.400s | 3136.447us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| quad_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| dual_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 50.360s | 15953.020us | 1 | 1 | 100.00 | |
| 4b_3b_feature | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 0.960s | 296.489us | 1 | 1 | 100.00 | |
| write_enable_disable | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 0.960s | 296.489us | 1 | 1 | 100.00 | |
| flash_mode_ignore_cmds | 1 | 1 | 100.00 | |||
| spi_device_flash_mode_ignore_cmds | 8.470s | 2962.879us | 1 | 1 | 100.00 | |
| TPM_with_flash_or_passthrough_mode | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 49.350s | 28105.062us | 1 | 1 | 100.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm_min_idle | 23.640s | 2889.650us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_device_stress_all | 0.580s | 60.463us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_device_alert_test | 0.370s | 29.696us | 1 | 1 | 100.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| spi_device_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| spi_device_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| spi_device_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| spi_device_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| spi_device_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| spi_device_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| spi_device_sec_cm | 0.580s | 89.274us | 1 | 1 | 100.00 | |
| spi_device_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| spi_device_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 11 test runs | |||
| spi_device_tl_errors | 36720796923983937314628251864824489229330063516963918709692024118759452652163 | None | ||
| spi_device_tl_intg_err | 95643758102231647286167974120853085350411843047326549645629637044742525086714 | None | ||
| spi_device_intr_test | 52628049557492636378407870991533898879369611250387742634497202464410880481400 | None | ||
| spi_device_mem_walk | 8236111404918358287584091874858065916579534711414415776404077777995613007462 | None | ||
| spi_device_mem_partial_access | 97313995179007562863247131865841110931550796946673455819664299893516020995582 | None | ||
| spi_device_csr_hw_reset | 7018166985743479815608369699082227506852069686771688295460266354892644990816 | None | ||
| spi_device_csr_rw | 95892276315739928511426379716098947190664374169458117144734261374647459652505 | None | ||
| spi_device_csr_bit_bash | 34037387216918637627948690929160461474096255911755850765858849601635876880688 | None | ||
| spi_device_csr_aliasing | 18162763670352517363972724846398525020770491386772267158412185242618931135374 | None | ||
| spi_device_same_csr_outstanding | 103764991288465519526176841919750719478457838663384292185274649868775873764575 | None | ||
| spi_device_csr_mem_rw_with_rand_reset | 58747547991557136688779061221884871411135213127556510980503958645559543090989 | None | ||
| Job returned a non-zero exit code: * | 1 test run | |||
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.105 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) | 1 test run | |||
| spi_device_mem_parity | 30190281171379158817651597631512906063661346395388155179148887021335469760074 | 76 |
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2233818 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2233818 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[940])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
|
|
| UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) | 1 test run | |||
| spi_device_ram_cfg | 112603373398868299008905142266969198048001298900564073567950295195664944464327 | 76 |
UVM_ERROR @ 819242 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1f [11111] vs 0x0 [0])
UVM_ERROR @ 884242 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa6 [10100110] vs 0x0 [0])
UVM_ERROR @ 887242 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e4 [1011100100] vs 0x0 [0])
UVM_ERROR @ 939242 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9 [1001] vs 0x0 [0])
|
|