Simulation Results: sram_ctrl/main

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.40 %
  • code
  • 94.32 %
  • assert
  • 97.69 %
  • func
  • 91.20 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
87.50%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 377.824us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 184.073us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.000s 30.624us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 193.217us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.967us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 375.189us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.000s 30.624us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.967us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 78.000s 11710.415us 1 1 100.00
mem_partial_access 0 1 0.00
sram_ctrl_mem_partial_access 73.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 23.000s 137005.046us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 128.000s 5230.302us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 112.000s 65954.022us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 29.000s 12030.494us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 23.000s 29692.046us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 3.000s 3247.618us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 3438.694us 1 1 100.00
sram_ctrl_partial_access_b2b 141.000s 52433.827us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 3704.499us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 689.665us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 1354.498us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 885.036us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 804.876us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 1.000s 377.824us 1 1 100.00
sram_ctrl_partial_access 3.000s 3438.694us 1 1 100.00
sram_ctrl_access_during_key_req 29.000s 12030.494us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 152.000s 77727.796us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 40.800us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.000s 332.199us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.000s 332.199us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 184.073us 1 1 100.00
sram_ctrl_csr_rw 0.000s 30.624us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.967us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 20.820us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 184.073us 1 1 100.00
sram_ctrl_csr_rw 0.000s 30.624us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.967us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 20.820us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.000s 15355.528us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 7.000s 1243.892us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 587.867us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 7.000s 1243.892us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 587.867us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 885.036us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 885.036us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.000s 30.624us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 3.000s 3247.618us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 3247.618us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 3247.618us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 23.000s 29692.046us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.000s 15355.528us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3602.028s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 377.824us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 377.824us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 3.000s 3247.618us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 7.000s 1243.892us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 23.000s 29692.046us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 7.000s 1243.892us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 7.000s 1243.892us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 377.824us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 7.000s 1243.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 9.000s 751.395us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 60284858375305036153960383788382166083359589733872546749582673589884991862498 None
sram_ctrl_mubi_enc_err 25223882903427980070876306678775368179703027409112928450968651937469278941963 None
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
sram_ctrl_mem_partial_access 73968350612458144582210868956666085969423156150631401404549360341568862909051 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 08, 2026 at 16:53:19 UTC (total: 00:01:13)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2