Simulation Results: sram_ctrl/ret

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.16 %
  • code
  • 80.27 %
  • assert
  • 97.40 %
  • func
  • 92.80 %
  • block
  • 90.29 %
  • line
  • 91.46 %
  • branch
  • 84.62 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 11.000s 83.972us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 54.278us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.249us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 98.062us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 6.000s 15.241us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 36.114us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.249us 1 1 100.00
sram_ctrl_csr_aliasing 6.000s 15.241us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 3.000s 410.460us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.000s 766.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 234.969us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 131.000s 3028.974us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 9.000s 815.757us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 691.406us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.000s 871.692us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 4.000s 880.986us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 11.000s 92.723us 1 1 100.00
sram_ctrl_partial_access_b2b 129.000s 22792.895us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 83.277us 1 1 100.00
sram_ctrl_throughput_w_partial_write 13.000s 53.732us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 61.336us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 16.000s 1334.160us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.000s 44.215us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 11.000s 83.972us 1 1 100.00
sram_ctrl_partial_access 11.000s 92.723us 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 691.406us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 20.000s 2728.816us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 6.000s 20.597us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 31.042us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 31.042us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 54.278us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.249us 1 1 100.00
sram_ctrl_csr_aliasing 6.000s 15.241us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.808us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 54.278us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.249us 1 1 100.00
sram_ctrl_csr_aliasing 6.000s 15.241us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.000s 913.223us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 11.000s 2557.371us 1 1 100.00
sram_ctrl_tl_intg_err 16.000s 404.311us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 11.000s 2557.371us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 16.000s 404.311us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 16.000s 1334.160us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 16.000s 1334.160us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.249us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 4.000s 880.986us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 880.986us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 880.986us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.000s 871.692us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.000s 913.223us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3602.021s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 11.000s 83.972us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 11.000s 83.972us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 4.000s 880.986us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 11.000s 2557.371us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.000s 871.692us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 11.000s 2557.371us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 11.000s 2557.371us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 11.000s 83.972us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 11.000s 2557.371us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 18.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 43714734735141902620175285541764931603766739241020467447680751888956038822069 None
sram_ctrl_mubi_enc_err 85323302950895231849767710047593105993518406078494484236590314715800875908363 None
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
sram_ctrl_stress_all_with_rand_reset 185937384248676040547592573529654288763859473584981931244045513697429258296 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 08, 2026 at 17:16:13 UTC (total: 00:00:18)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2