Simulation Results: uart

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 77.68 %
  • code
  • 91.74 %
  • assert
  • 97.12 %
  • func
  • 44.18 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.68 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.660s 327.367us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.310s 16.612us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.310s 95.608us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.170s 354.343us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.310s 15.252us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.370s 104.355us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.310s 95.608us 1 1 100.00
uart_csr_aliasing 0.310s 15.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 4.190s 13700.145us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.660s 327.367us 1 1 100.00
uart_tx_rx 4.190s 13700.145us 1 1 100.00
parity_error 2 2 100.00
uart_intr 44.900s 68399.081us 1 1 100.00
uart_rx_parity_err 14.740s 30680.539us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 4.190s 13700.145us 1 1 100.00
uart_intr 44.900s 68399.081us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 30.850s 64677.556us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 82.810s 119115.190us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 27.300s 178719.102us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 44.900s 68399.081us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 44.900s 68399.081us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 44.900s 68399.081us 1 1 100.00
perf 1 1 100.00
uart_perf 116.730s 13497.399us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 8.500s 10687.749us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 8.500s 10687.749us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.810s 592.898us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 0.530s 1302.089us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 4.050s 6526.242us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 0.420s 1832.146us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 43.080s 217668.811us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 105.940s 289618.535us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.290s 13.818us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.320s 24.581us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.030s 117.948us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.030s 117.948us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.310s 16.612us 1 1 100.00
uart_csr_rw 0.310s 95.608us 1 1 100.00
uart_csr_aliasing 0.310s 15.252us 1 1 100.00
uart_same_csr_outstanding 0.350s 259.942us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.310s 16.612us 1 1 100.00
uart_csr_rw 0.310s 95.608us 1 1 100.00
uart_csr_aliasing 0.310s 15.252us 1 1 100.00
uart_same_csr_outstanding 0.350s 259.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.420s 74.610us 1 1 100.00
uart_tl_intg_err 0.600s 83.381us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.600s 83.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 17.110s 2205.321us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_noise_filter 80495017703043171141202478882765772694762806774203090861583237576192967797884 80
UVM_ERROR @ 100848286 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 138118286 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4, clk_pulses: 0
UVM_ERROR @ 138138286 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 138178286 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:444) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty 1 test run
uart_stress_all_with_rand_reset 56026347221269512419463623148935938100137446210584859044111422376490881347535 104
UVM_INFO @ 456391454 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/288
UVM_INFO @ 560781454 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/288
UVM_INFO @ 580241454 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/288
UVM_INFO @ 689931454 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/288
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_stress_all 10518664783459589069926632847740705772371960322233921668181111653504939389845 117
UVM_ERROR @ 288391774589 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 288391934589 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (156 [0x9c] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 288392014589 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 288392134589 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (156 [0x9c] vs 255 [0xff]) reg name: uart_reg_block.rdata