Simulation Results: adc_ctrl

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.53 %
  • code
  • 96.78 %
  • assert
  • 96.43 %
  • func
  • 18.39 %
  • line
  • 99.05 %
  • branch
  • 98.45 %
  • cond
  • 94.50 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.290s 5734.748us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.080s 1349.999us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.550s 335.158us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 67.230s 44053.581us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 0.730s 540.824us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.200s 497.748us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.550s 335.158us 1 1 100.00
adc_ctrl_csr_aliasing 0.730s 540.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 11.640s 38872.423us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 45.840s 36541.367us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 6.990s 18154.298us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 9.720s 35404.776us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 19.830s 73999.481us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 82.300s 71873.258us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 14.660s 51118.138us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.820s 1845.273us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.400s 3673.440us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 37.730s 29281.958us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 74.230s 62541.253us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 29.130s 49624.849us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.770s 354.291us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.730s 316.607us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.670s 812.679us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.670s 812.679us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.080s 1349.999us 1 1 100.00
adc_ctrl_csr_rw 0.550s 335.158us 1 1 100.00
adc_ctrl_csr_aliasing 0.730s 540.824us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.490s 2404.122us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.080s 1349.999us 1 1 100.00
adc_ctrl_csr_rw 0.550s 335.158us 1 1 100.00
adc_ctrl_csr_aliasing 0.730s 540.824us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.490s 2404.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 4.090s 3956.468us 1 1 100.00
adc_ctrl_tl_intg_err 2.970s 8935.936us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.970s 8935.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 2.650s 8216.217us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
adc_ctrl_clock_gating 51547628567474655726854254587147591909876035226501210944890228017600934130786 392
UVM_INFO @ 1845273452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---