Simulation Results: aes/unmasked

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.02 %
  • code
  • 89.66 %
  • assert
  • 97.73 %
  • func
  • 76.67 %
  • block
  • 89.40 %
  • line
  • 91.82 %
  • branch
  • 79.95 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 76.389us 1 1 100.00
smoke 1 1 100.00
aes_smoke 0.000s 65.485us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 71.390us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 77.403us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 2143.644us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 0.000s 117.156us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 86.654us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 77.403us 1 1 100.00
aes_csr_aliasing 0.000s 117.156us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 0.000s 65.485us 1 1 100.00
aes_config_error 1.000s 66.129us 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
key_length 3 3 100.00
aes_smoke 0.000s 65.485us 1 1 100.00
aes_config_error 1.000s 66.129us 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
back2back 2 2 100.00
aes_stress 1.000s 64.212us 1 1 100.00
aes_b2b 4.000s 287.682us 1 1 100.00
backpressure 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 0.000s 65.485us 1 1 100.00
aes_config_error 1.000s 66.129us 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
aes_alert_reset 1.000s 109.183us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 64.313us 1 1 100.00
aes_config_error 1.000s 66.129us 1 1 100.00
aes_alert_reset 1.000s 109.183us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 1.000s 255.310us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 2.000s 135.215us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 1.000s 109.183us 1 1 100.00
stress 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
sideload 2 2 100.00
aes_stress 1.000s 64.212us 1 1 100.00
aes_sideload 1.000s 81.666us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 816.885us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 2.000s 205.425us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 66.838us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 96.369us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 96.369us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 71.390us 1 1 100.00
aes_csr_rw 1.000s 77.403us 1 1 100.00
aes_csr_aliasing 0.000s 117.156us 1 1 100.00
aes_same_csr_outstanding 1.000s 141.363us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 71.390us 1 1 100.00
aes_csr_rw 1.000s 77.403us 1 1 100.00
aes_csr_aliasing 0.000s 117.156us 1 1 100.00
aes_same_csr_outstanding 1.000s 141.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 18.285us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_cipher_fi 1.000s 47.824us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 133.917us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 133.917us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 133.917us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 133.917us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 1.000s 152.675us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 808.937us 1 1 100.00
aes_tl_intg_err 1.000s 527.804us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 527.804us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 1.000s 109.183us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 133.917us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 133.917us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 0.000s 65.485us 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
aes_alert_reset 1.000s 109.183us 1 1 100.00
aes_core_fi 1.000s 82.818us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 1.000s 66.129us 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
aes_core_fi 1.000s 82.818us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 133.917us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 52.692us 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 1.000s 64.212us 1 1 100.00
aes_sideload 1.000s 81.666us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 52.692us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 52.692us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 52.692us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 52.692us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 52.692us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 1.000s 64.212us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 153.699us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_cipher_fi 1.000s 47.824us 1 1 100.00
aes_ctr_fi 1.000s 54.615us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 153.699us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_cipher_fi 1.000s 47.824us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 47.824us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 153.699us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_ctr_fi 1.000s 54.615us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 153.699us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_cipher_fi 1.000s 47.824us 1 1 100.00
aes_ctr_fi 1.000s 54.615us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 1.000s 109.183us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_cipher_fi 1.000s 47.824us 1 1 100.00
aes_ctr_fi 1.000s 54.615us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_cipher_fi 1.000s 47.824us 1 1 100.00
aes_ctr_fi 1.000s 54.615us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_ctr_fi 1.000s 54.615us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 153.699us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 153.699us 0 1 0.00
aes_control_fi 1.000s 50.981us 1 1 100.00
aes_cipher_fi 1.000s 47.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 123.685us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 707575212748843879255034453306133197265554225275354881864187510739992040858 5391
UVM_INFO @ 18285069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 107882125769139149767152241824207001753552488162151729096815406426290097835465 4654
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 95038727825453350235739404901881138048628252457547606086354397830621638092961 158
UVM_INFO @ 123684765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---