Simulation Results

Simulation Results: chip

09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
70.31 %

code
76.03 %

assert
96.86 %

func
38.03 %

line
93.70 %

branch
93.23 %

cond
90.05 %

toggle
69.86 %

FSM
33.33 %

Validation stages

V1		100.00%
V2		85.55%
V2S		100.00%
V3		56.00%
unmapped		12.50%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	68.440s	2208.039us	1	1	100.00
	chip_sw_example_manufacturer	155.780s	2771.801us	1	1	100.00
	chip_sw_example_concurrency	207.820s	3006.607us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	295.980s	10567.999us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	507.130s	11117.102us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	1754.210s	33848.041us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	9592.770s	89645.652us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	610.840s	12858.447us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	9592.770s	89645.652us	1	1	100.00
	chip_csr_rw	507.130s	11117.102us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	3.400s	54.031us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	301.980s	4173.244us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	301.980s	4173.244us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	301.980s	4173.244us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	338.950s	3908.307us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	338.950s	3908.307us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	418.040s	4743.586us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	353.940s	4204.178us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	335.550s	3784.493us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1672.770s	12921.000us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	353.100s	3997.621us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	656.670s	8417.465us	1	1	100.00

225/263 passed

85.55 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	274.170s	9307.404us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	274.170s	9307.404us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	237.290s	3027.119us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	350.220s	6381.722us	1	1	100.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	206.070s	3148.622us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	91.830s	2830.626us	1	1	100.00
	chip_tap_straps_testunlock0	218.560s	5283.335us	1	1	100.00
	chip_tap_straps_rma	240.660s	5942.889us	1	1	100.00
	chip_tap_straps_prod	349.220s	6972.215us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	440.220s	5111.247us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	440.220s	5111.247us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	623.500s	7836.994us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1678.390s	13558.471us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3631.090s	18667.936us	1	1	100.00
	chip_sw_aes_enc_jitter_en	165.770s	2560.201us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	643.440s	6505.155us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	151.550s	2330.938us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	672.800s	6757.334us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	209.100s	2691.252us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	396.210s	3997.778us	1	1	100.00
	chip_sw_clkmgr_jitter	160.730s	2606.092us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	209.000s	2885.278us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	412.620s	5414.265us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	133.740s	2681.082us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	137.420s	3102.039us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	133.740s	2681.082us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	192.380s	2946.798us	1	1	100.00
	chip_sw_aon_timer_smoketest	167.760s	3051.632us	1	1	100.00
	chip_sw_clkmgr_smoketest	149.640s	2611.512us	1	1	100.00
	chip_sw_csrng_smoketest	186.210s	2920.022us	1	1	100.00
	chip_sw_entropy_src_smoketest	630.460s	5609.185us	1	1	100.00
	chip_sw_gpio_smoketest	198.340s	3148.276us	1	1	100.00
	chip_sw_hmac_smoketest	247.650s	3592.134us	1	1	100.00
	chip_sw_kmac_smoketest	193.010s	2679.973us	1	1	100.00
	chip_sw_otbn_smoketest	1094.650s	8057.149us	1	1	100.00
	chip_sw_pwrmgr_smoketest	257.420s	4947.755us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	314.900s	5038.564us	1	1	100.00
	chip_sw_rv_plic_smoketest	130.770s	2868.274us	1	1	100.00
	chip_sw_rv_timer_smoketest	179.780s	3189.242us	1	1	100.00
	chip_sw_rstmgr_smoketest	111.870s	2147.073us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	175.930s	2736.977us	1	1	100.00
	chip_sw_uart_smoketest	176.160s	2725.702us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	168.250s	2286.419us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	367.500s	4985.615us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	18723.720s	128139.967us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3324.570s	17852.966us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	259.760s	8600.513us	0	1	0.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	371.670s	3791.325us	1	1	100.00
chip_sw_power_sleep_load				1	1	100.00
	chip_sw_power_sleep_load	309.130s	9837.844us	1	1	100.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.055s	0.000us	0	1	0.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	439.730s	10844.957us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	439.730s	10844.957us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	9592.770s	89645.652us	1	1	100.00
	chip_same_csr_outstanding	1531.620s	21904.053us	1	1	100.00
	chip_csr_hw_reset	295.980s	10567.999us	1	1	100.00
	chip_csr_rw	507.130s	11117.102us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	9592.770s	89645.652us	1	1	100.00
	chip_same_csr_outstanding	1531.620s	21904.053us	1	1	100.00
	chip_csr_hw_reset	295.980s	10567.999us	1	1	100.00
	chip_csr_rw	507.130s	11117.102us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	7.380s	256.397us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	3.240s	39.345us	1	1	100.00
	xbar_smoke_large_delays	35.140s	9160.229us	1	1	100.00
	xbar_smoke_slow_rsp	31.510s	5205.428us	1	1	100.00
	xbar_random_zero_delays	8.800s	128.188us	1	1	100.00
	xbar_random_large_delays	163.990s	39873.759us	1	1	100.00
	xbar_random_slow_rsp	127.560s	21312.084us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	3.810s	71.439us	1	1	100.00
	xbar_error_and_unmapped_addr	14.010s	525.281us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	33.420s	1823.922us	1	1	100.00
	xbar_error_and_unmapped_addr	14.010s	525.281us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	75.770s	3059.984us	1	1	100.00
	xbar_access_same_device_slow_rsp	117.730s	18795.015us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	3.220s	31.520us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	64.000s	2236.018us	1	1	100.00
	xbar_stress_all_with_error	51.230s	2408.278us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	57.030s	184.441us	1	1	100.00
	xbar_stress_all_with_reset_error	50.710s	356.544us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3324.570s	17852.966us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2665.900s	34057.727us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3542.210s	26643.667us	1	1	100.00
rom_e2e_boot_policy_valid				15	15	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2520.520s	10884.881us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3361.560s	15390.662us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	3293.670s	16087.151us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3061.480s	16211.167us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3021.710s	14560.137us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2462.160s	11173.800us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3268.600s	16245.133us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3278.040s	16027.524us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	3283.490s	16258.402us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	3080.320s	15451.000us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	4599.040s	17566.882us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	5622.400s	24045.257us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	6029.280s	25099.098us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	5723.110s	27414.897us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	5770.430s	23805.528us	1	1	100.00
rom_e2e_sigverify_always				15	15	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	4412.150s	17441.270us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	5919.680s	31779.486us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	5791.660s	23840.658us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	5942.360s	30859.744us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	5782.100s	29076.475us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	2540.610s	18383.562us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3413.030s	24621.866us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	3405.210s	22225.478us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	3124.210s	26697.486us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3077.760s	19208.634us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2804.470s	36036.057us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	3326.390s	18471.696us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	3356.920s	28019.974us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	2914.110s	13765.871us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3155.110s	23508.628us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	2481.630s	11596.684us	1	1	100.00
	rom_e2e_asm_init_dev	3311.510s	15663.799us	1	1	100.00
	rom_e2e_asm_init_prod	3176.180s	17730.633us	1	1	100.00
	rom_e2e_asm_init_prod_end	3330.800s	16292.469us	1	1	100.00
	rom_e2e_asm_init_rma	3280.290s	16203.743us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	6760.470s	29219.715us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	6621.630s	32389.986us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	6320.870s	28780.574us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3635.060s	18703.522us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3141.960s	34229.295us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3141.960s	34229.295us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	179.100s	2817.815us	1	1	100.00
	chip_sw_aes_enc_jitter_en	165.770s	2560.201us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	178.210s	2619.462us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	189.850s	2858.555us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1105.560s	8128.600us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	152.790s	2354.318us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	392.850s	5384.342us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	391.730s	5321.351us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	462.160s	4375.148us	1	1	100.00
	chip_plic_all_irqs_10	244.310s	3106.361us	1	1	100.00
	chip_plic_all_irqs_20	338.290s	3441.285us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	148.810s	2753.970us	0	1	0.00
chip_sw_alert_handler_crashdump				0	1	0.00
	chip_sw_rstmgr_alert_info	1009.160s	9649.433us	0	1	0.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	170.240s	3103.220us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	124.820s	2362.520us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	197.190s	2921.974us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1111.330s	9055.968us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	786.570s	6776.948us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	812.600s	8062.691us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8395.680s	255481.320us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	229.570s	3597.264us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	257.420s	4947.755us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	229.570s	3597.264us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	523.550s	7571.429us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	523.550s	7571.429us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	286.990s	7256.641us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	456.580s	5296.735us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	613.790s	6148.031us	1	1	100.00
	chip_sw_aes_idle	189.850s	2858.555us	1	1	100.00
	chip_sw_hmac_enc_idle	207.220s	2663.742us	1	1	100.00
	chip_sw_kmac_idle	168.170s	2717.393us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	195.000s	3143.269us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	204.430s	4027.463us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	276.720s	4619.814us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	200.980s	3188.107us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	589.950s	9024.977us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	359.100s	4329.624us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	397.840s	4955.454us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	373.100s	4056.667us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	422.890s	4355.697us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	423.500s	4535.703us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	357.260s	4203.078us	1	1	100.00
	chip_sw_ast_clk_outputs	623.500s	7836.994us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	710.800s	16395.376us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	373.100s	4056.667us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	422.890s	4355.697us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3631.090s	18667.936us	1	1	100.00
	chip_sw_aes_enc_jitter_en	165.770s	2560.201us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	643.440s	6505.155us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	151.550s	2330.938us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	672.800s	6757.334us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	209.100s	2691.252us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	396.210s	3997.778us	1	1	100.00
	chip_sw_clkmgr_jitter	160.730s	2606.092us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	163.770s	3002.449us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3623.720s	25109.104us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	162.180s	3170.839us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	160.150s	3027.446us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	939.310s	9559.952us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	191.060s	3227.098us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	358.750s	5128.079us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	7263.860s	55643.088us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	623.500s	7836.994us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	360.050s	4774.000us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	504.320s	10174.088us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	391.730s	5321.351us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1111.330s	9055.968us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	792.590s	5791.029us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	298.900s	4147.906us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	572.730s	8534.681us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	159.040s	2787.605us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3013.490s	17003.240us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	158.510s	2498.912us	1	1	100.00
	chip_sw_edn_entropy_reqs	638.510s	5522.187us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	158.510s	2498.912us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	792.590s	5791.029us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	148.910s	2450.034us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	167.870s	3125.403us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	151.550s	2330.938us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	207.220s	2663.742us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1393.680s	9470.549us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1805.790s	12010.100us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	322.370s	4534.247us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	499.110s	5325.159us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	467.410s	5642.732us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	322.580s	3997.682us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	1089.570s	8961.790us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	672.800s	6757.334us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	1841.880s	11757.494us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1105.560s	8128.600us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.046s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	142.680s	2998.883us	1	1	100.00
	chip_sw_kmac_mode_kmac	198.270s	3223.882us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	209.100s	2691.252us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1089.570s	8961.790us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	780.930s	16617.619us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	326.340s	7212.817us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1639.960s	11253.817us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	168.170s	2717.393us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	392.850s	5384.342us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	91.830s	2830.626us	1	1	100.00
	chip_tap_straps_rma	240.660s	5942.889us	1	1	100.00
	chip_tap_straps_prod	349.220s	6972.215us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	151.890s	2944.427us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	780.930s	16617.619us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	780.930s	16617.619us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	780.930s	16617.619us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	1473.190s	10529.258us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	271.200s	10010.280us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	250.120s	3454.471us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	637.560s	6983.730us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	487.590s	5555.585us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	622.430s	6695.612us	0	1	0.00
	chip_sw_lc_ctrl_transition	780.930s	16617.619us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	311.440s	4427.857us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1089.570s	8961.790us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	547.200s	19721.920us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	551.230s	7610.721us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	710.800s	16395.376us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	359.100s	4329.624us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	397.840s	4955.454us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	373.100s	4056.667us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	422.890s	4355.697us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	423.500s	4535.703us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	357.260s	4203.078us	1	1	100.00
	chip_tap_straps_dev	91.830s	2830.626us	1	1	100.00
	chip_tap_straps_rma	240.660s	5942.889us	1	1	100.00
	chip_tap_straps_prod	349.220s	6972.215us	1	1	100.00
	chip_rv_dm_lc_disabled	33.610s	1541.223us	0	1	0.00
chip_lc_scrap				2	4	50.00
	chip_sw_lc_ctrl_rma_to_scrap	313.680s	6608.193us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	308.240s	10452.595us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	378.210s	10811.462us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	351.000s	9551.107us	0	1	0.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	2752.460s	60000.000us	0	1	0.00
	chip_rv_dm_lc_disabled	33.610s	1541.223us	0	1	0.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	719.320s	25985.044us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1081.950s	20110.043us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	1081.630s	14797.561us	1	1	100.00
	chip_sw_lc_walkthrough_rma	601.720s	13604.853us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	2752.460s	60000.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	116.180s	4255.325us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	169.000s	6011.138us	1	1	100.00
	rom_volatile_raw_unlock	137.100s	4218.844us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3529.300s	17858.827us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3631.090s	18667.936us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	613.790s	6148.031us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	613.790s	6148.031us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	613.790s	6148.031us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	287.210s	3504.843us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	780.930s	16617.619us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	287.210s	3504.843us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1089.570s	8961.790us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	362.890s	4767.361us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	2933.910s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	287.210s	3504.843us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1089.570s	8961.790us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	362.890s	4767.361us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	2933.910s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	780.930s	16617.619us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	350.410s	5676.360us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	151.890s	2944.427us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	250.120s	3454.471us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	637.560s	6983.730us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	487.590s	5555.585us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	622.430s	6695.612us	0	1	0.00
	chip_sw_lc_ctrl_transition	780.930s	16617.619us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	840.690s	6784.339us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	274.080s	6043.829us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	128.890s	2637.711us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	106.960s	2260.238us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	466.340s	9127.002us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	224.650s	4950.482us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	788.920s	21675.103us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	540.650s	10190.063us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	523.550s	7571.429us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	184.340s	3669.694us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	350.370s	4422.821us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	274.080s	6043.829us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	357.080s	4842.454us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	871.180s	15811.691us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	339.400s	6719.540us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	107.310s	2292.389us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	351.530s	6844.086us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	500.160s	6076.643us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1079.110s	9822.401us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1117.120s	20719.661us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	208.070s	3566.692us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	391.730s	5321.351us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	547.200s	19721.920us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	547.200s	19721.920us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1079.110s	9822.401us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	351.530s	6844.086us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	350.370s	4422.821us	1	1	100.00
	chip_sw_pwrmgr_smoketest	257.420s	4947.755us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	347.360s	5309.042us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	480.220s	5808.428us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	264.990s	4701.243us	1	1	100.00
chip_sw_rstmgr_alert_info				0	1	0.00
	chip_sw_rstmgr_alert_info	1009.160s	9649.433us	0	1	0.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	205.710s	3249.911us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	391.730s	5321.351us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	786.570s	6776.948us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	515.060s	5101.100us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	506.050s	4360.604us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	183.430s	3117.653us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	2933.910s	60000.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	480.220s	5808.428us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	480.220s	5808.428us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	120.990s	2221.595us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	622.000s	15155.645us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	1043.010s	23057.470us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	347.360s	5309.042us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	223.740s	2950.069us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	190.990s	3005.295us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	240.660s	5942.889us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	33.610s	1541.223us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	462.160s	4375.148us	1	1	100.00
	chip_plic_all_irqs_10	244.310s	3106.361us	1	1	100.00
	chip_plic_all_irqs_20	338.290s	3441.285us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	166.530s	2891.220us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	155.320s	2834.160us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3324.570s	17852.966us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	362.600s	6240.739us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	204.840s	3192.840us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	168.820s	3071.760us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	202.410s	2855.830us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	362.890s	4767.361us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	396.210s	3997.778us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	196.370s	2807.550us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	197.410s	2903.584us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	551.230s	7610.721us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	391.730s	5321.351us	1	1	100.00
	chip_sw_data_integrity_escalation	440.220s	5111.247us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	500.160s	6076.643us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	949.400s	22292.680us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	168.000s	2689.049us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	224.060s	4015.916us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	326.600s	4338.795us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	949.400s	22292.680us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	949.400s	22292.680us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2340.540s	20495.582us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2340.540s	20495.582us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	296.080s	5855.111us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3141.960s	34229.295us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	157.790s	2706.501us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	152.510s	3234.714us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	246.630s	3328.964us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	329.590s	3888.720us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	967.310s	8343.171us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	4917.400s	31493.110us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1740.630s	11945.538us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	173.770s	2539.381us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	153.830s	2628.860us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	157.700s	2276.373us	1	1	100.00

14/25 passed

56.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	11741.690s	72046.071us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1208.190s	6625.981us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	49.030s	2175.014us	0	1	0.00
	rom_e2e_jtag_debug_dev	54.750s	2084.503us	0	1	0.00
	rom_e2e_jtag_debug_rma	48.870s	1749.764us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	63.950s	2392.182us	0	1	0.00
	rom_e2e_jtag_inject_dev	56.560s	2721.813us	0	1	0.00
	rom_e2e_jtag_inject_rma	185.800s	3476.424us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	16.908s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	226.200s	3004.360us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	316.670s	2873.788us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	1016.680s	5815.087us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1086.810s	8281.724us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	246.230s	2369.089us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	179.850s	2404.358us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	330.590s	5317.018us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	298.020s	4774.724us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1079.110s	9822.401us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	326.340s	7212.817us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	49.030s	2175.014us	0	1	0.00
	rom_e2e_jtag_debug_dev	54.750s	2084.503us	0	1	0.00
	rom_e2e_jtag_debug_rma	48.870s	1749.764us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				0	1	0.00
	chip_sw_rv_dm_access_after_escalation_reset	191.470s	2904.373us	0	1	0.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	391.730s	5321.351us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5411.400s	38173.787us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5411.400s	38173.787us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	147.790s	2527.243us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	338.950s	3908.307us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3098.350s	18702.328us	1	1	100.00

unmapped

1/8 passed

12.50 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	8	12.50
	chip_sw_rstmgr_rst_cnsty_escalation	27.210s	10.140us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	54.530s	1796.775us	0	1	0.00
	chip_sw_otp_ctrl_descrambling	167.230s	2767.721us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	142.890s	3004.969us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	6.277s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	561.400s	10010.260us	0	1	0.00
	ate_bootstrap_one_frame	10800.032s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.041s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				13 test runs
	chip_sw_sleep_pin_retention	63879089962290272680914026437230073490923200291410592511771753266201763023969	379	UVM_INFO @ 3148.621572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	36259203198903881539360961769532102224076276460213343835450603700924555199692	374	UVM_INFO @ 2527.242608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	41826200335968169582689992477236886279393334034611785019465334902172693490596	392	UVM_INFO @ 6844.085816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	103849485345213053746432817383044199573978634132169237867897159230706821220825	377	UVM_INFO @ 3669.694482 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	26866664390054457616322515041582584759958036523546333832016196115923529144072	388	UVM_INFO @ 4950.481908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	36458134105468546043535219317927568677012274625848232797394087534236937847845	377	UVM_INFO @ 2807.549658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	95973843882296085162783109082038702274580912582618601763226662236488884924423	381	UVM_INFO @ 2903.584122 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	54721420045821821909595785967664962533724533240825756109684383569888356861637	372	UVM_INFO @ 2681.082236 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	84632151662004582033847826802222959869730773338168198210809605920011043917883	407	UVM_INFO @ 4774.000248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	61549552399827847430217599195683603388286800172960481157589161711252183543668	374	UVM_INFO @ 2260.238410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	30515771252863552822820858842835236212031181428658711203983498762571421676169	372	UVM_INFO @ 3004.969224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	82549475376354662864291118648914640503362711752056282254264327454397655599691	373	UVM_INFO @ 2637.710780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	53661949458455827443277972094354235792032595614189589403566372308626645936673	390	UVM_INFO @ 3005.294936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				5 test runs
	chip_sw_otp_ctrl_rot_auth_config	89652641322251918493017281356442995189806415417834277518618122104561877702441	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	88167064430396697561379576936137079568682497913099374462305367055181618648334	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	619955830090114656863890490905535760087853262017978501765033810462328419518	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	89577843893652460752089082645034116840645098529675995563063593573086792352201	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	97392052803898742783865050761237047843311395282942425455906608301309687428121	386	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
Job timed out after * minutes				4 test runs
	chip_sw_exit_test_unlocked_bootstrap	27340038925201313507967785422504757086703035496353982253263669447776124123935	None
	chip_sw_keymgr_dpe_sideload_otbn	17146342608574458322298552606542096398581335896213384379104540571839305124273	None
	ate_bootstrap_one_frame	28440256200094193302818984760440308788507613766821478424288082566196249155053	None
	ate_bootstrap_disjoint	8483714863657417025621242129112852835159857687658166176274373544826740059558	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				3 test runs
	chip_sw_rstmgr_alert_info	36566349860832500636565889382453318652641128596590857619732555584231804063708	946	UVM_INFO @ 9649.432822 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_lpg_sleep_mode_pings	35191654502365160852539160082038678429021256750200167641176903149060745842836	374	UVM_INFO @ 2921.974476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	53759530712015812426620154234483182471212611238136443195287046523014631939507	445	UVM_INFO @ 2753.969856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	91128593356907245913797481631029760665815772990531189708543698873805612659511	359	UVM_INFO @ 2175.013500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	77991490619581860358196005529040972578373744144236507618669762970291917605405	359	UVM_INFO @ 2084.503000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	67393393127108785281982119033736564827565786591179334458952869961769556034410	359	UVM_INFO @ 1749.764000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				2 test runs
	chip_sw_lc_ctrl_test_locked0_to_scrap	29549199534426128018227668977251628308929636197752150158276520824354193367075	375	UVM_INFO @ 10811.462267 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_ctrl_rand_to_scrap	51201727826384899426307257910830673402902998899570249550425671633999666989171	375	UVM_INFO @ 9551.107192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				2 test runs
	chip_sw_lc_walkthrough_prod	21789015243429454781792500612664989652142257602352305489976730530476992568850	433	UVM_INFO @ 20110.042846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	15092495168856972326325337931955121592266936363575227264147906888609130410567	405	UVM_INFO @ 13604.853370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue				2 test runs
	chip_sw_lc_walkthrough_testunlocks	10407126905103188116291449061539857807424749322829739204018866244535205738136	513	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_core_ibex_icache_invalidate	84062688077871715475899532707147283760091331956431931349183819251409191459035	377	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	1061208759916930139595666500838038519040463843970473767222836412264493277984	377	UVM_ERROR @ 2292.388864 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2292.388864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	15204193957620583162712996287917668215932726223664480355200171081999801639455	431	UVM_ERROR @ 15811.691010 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 15811.691010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	77831692319024883697650718228151379062840179240917442603381291214695798712707	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	17160346759223995920941571722860136521894393896219911855194437958602013931842	None	Another command (pid=503466) is running. Waiting for it to complete on the server (server_pid=190598)... Another command (pid=608251) is running. Waiting for it to complete on the server (server_pid=190598)... Another command (pid=613059) is running. Waiting for it to complete on the server (server_pid=190598)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	15927440402133875612472924028397097277898046599051698517602769046385006825505	365	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	61081432310507205455500169662071756106961294158766560956554735905586114894894	393	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	72427166445196891548184072251326346506095663472906438983759846443680009492826	337	UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	105002745943922134444964833433312895607177206895716662933307611362129124897143	404	UVM_INFO @ 6695.611794 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	4652402366515066848316195521088065891478168364742931164666687376930604653411	380	UVM_ERROR @ 2404.358450 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2404.358450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_walkthrough_dev	96651610236200123508663235521251198410811782219216050107868115301046288843050	372	UVM_INFO @ 25985.044339 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	103640200097114990629686829135355371824419186101251282985629247211435067231008	405	UVM_ERROR @ 10190.062800 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 10190.062800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	71429634895576717055546223221495312382221904948293487998015967021431899371000	396	UVM_INFO @ 34229.295031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	38107096092536403902348764305931222935400259835614427645450292018580975919252	371	UVM_INFO @ 2354.317682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	76714734372604547028639623850132390193367205844730546153213057794712105448416	373	UVM_INFO @ 2362.520204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_hmac_multistream	53056168469040155357519147245390454891438071511836621462278701133938316037533	417	UVM_INFO @ 12010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	49675390610099577646265537895797790757597743673170356125722722005995078539735	400	UVM_INFO @ 10174.088217 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	52639658520403641783763190131052808805584557118490866148627731678687568946812	407	UVM_INFO @ 3004.360456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)'				1 test run
	chip_sw_rv_dm_access_after_escalation_reset	52225885993540274992862781137198970172059541686639909407271575049721779713374	387	UVM_ERROR @ 2904.372840 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A UVM_INFO @ 2904.372840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	88226145593369250548137452194055947988051194952731309063958315290448727903135	292	UVM_INFO @ 1541.222832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	30391765976502355585140656161119748494690956854580646241950958686735461135551	391	UVM_INFO @ 13558.471347 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	74052904159862780308161035183659792396471602098805543132146157768725366184498	339	UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				1 test run
	rom_raw_unlock	24040624213144395253928269612075478340895839836975067958107197773083064574630	384	UVM_INFO @ 8600.512865 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---