Simulation Results: clkmgr

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 93.43 %
  • code
  • 98.61 %
  • assert
  • 95.06 %
  • func
  • 86.62 %
  • line
  • 99.24 %
  • branch
  • 99.06 %
  • cond
  • 95.06 %
  • toggle
  • 99.68 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.760s 48.588us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.650s 17.098us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.610s 29.229us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.930s 1176.610us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.780s 22.665us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.420s 39.745us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.610s 29.229us 1 1 100.00
clkmgr_csr_aliasing 0.780s 22.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.660s 41.036us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.820s 42.617us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.350s 327.345us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 32.548us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.760s 48.588us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 7.800s 2482.800us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.490s 989.145us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 7.800s 2482.800us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 10.640s 4600.899us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.840s 58.844us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.800s 252.286us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.800s 252.286us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.650s 17.098us 1 1 100.00
clkmgr_csr_rw 0.610s 29.229us 1 1 100.00
clkmgr_csr_aliasing 0.780s 22.665us 1 1 100.00
clkmgr_same_csr_outstanding 1.200s 55.889us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.650s 17.098us 1 1 100.00
clkmgr_csr_rw 0.610s 29.229us 1 1 100.00
clkmgr_csr_aliasing 0.780s 22.665us 1 1 100.00
clkmgr_same_csr_outstanding 1.200s 55.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 1.850s 179.736us 1 1 100.00
clkmgr_tl_intg_err 1.240s 124.837us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 171.698us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 171.698us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 171.698us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 171.698us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.890s 316.567us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.240s 124.837us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 7.800s 2482.800us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.490s 989.145us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 171.698us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.920s 32.341us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.920s 178.968us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.620s 21.513us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.750s 41.059us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.150s 199.726us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.610s 29.229us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 1.850s 179.736us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.610s 29.229us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.610s 29.229us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 1.850s 179.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 5.270s 1050.788us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 24.990s 3229.686us 1 1 100.00