Simulation Results: edn/edn0

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.39 %
  • code
  • 80.12 %
  • assert
  • 96.10 %
  • func
  • 79.96 %
  • line
  • 97.23 %
  • branch
  • 90.52 %
  • cond
  • 86.59 %
  • toggle
  • 77.34 %
  • FSM
  • 48.92 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.720s 17.984us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.660s 62.398us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.690s 17.960us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.510s 46.894us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.780s 20.309us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.880s 52.497us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.690s 17.960us 1 1 100.00
edn_csr_aliasing 0.780s 20.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.010s 45.275us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.010s 45.275us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.010s 45.275us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.720s 22.521us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.200s 30.517us 1 1 100.00
errs 1 1 100.00
edn_err 0.910s 220.316us 1 1 100.00
disable 2 2 100.00
edn_disable 0.810s 53.747us 1 1 100.00
edn_disable_auto_req_mode 1.110s 87.781us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.920s 432.007us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.700s 55.996us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.710s 32.531us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.540s 66.560us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.540s 66.560us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.660s 62.398us 1 1 100.00
edn_csr_rw 0.690s 17.960us 1 1 100.00
edn_csr_aliasing 0.780s 20.309us 1 1 100.00
edn_same_csr_outstanding 0.890s 107.855us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.660s 62.398us 1 1 100.00
edn_csr_rw 0.690s 17.960us 1 1 100.00
edn_csr_aliasing 0.780s 20.309us 1 1 100.00
edn_same_csr_outstanding 0.890s 107.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.490s 1540.122us 1 1 100.00
edn_tl_intg_err 1.600s 74.728us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.710s 36.978us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.200s 30.517us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.490s 1540.122us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.490s 1540.122us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.490s 1540.122us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.490s 1540.122us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.200s 30.517us 1 1 100.00
edn_sec_cm 4.490s 1540.122us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.200s 30.517us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.600s 74.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 70.470s 19870.118us 1 1 100.00