Simulation Results: edn/edn1

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 86.98 %
  • code
  • 82.10 %
  • assert
  • 98.18 %
  • func
  • 80.67 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 90.15 %
  • toggle
  • 87.80 %
  • FSM
  • 42.05 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.780s 47.161us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.620s 25.171us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 17.004us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.570s 1284.793us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.810s 16.953us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
edn_csr_mem_rw_with_rand_reset 45.720s 10004.467us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 17.004us 1 1 100.00
edn_csr_aliasing 0.810s 16.953us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.090s 231.937us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.090s 231.937us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.090s 231.937us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.900s 21.839us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.720s 112.997us 1 1 100.00
errs 1 1 100.00
edn_err 0.710s 76.725us 1 1 100.00
disable 2 2 100.00
edn_disable 0.580s 41.961us 1 1 100.00
edn_disable_auto_req_mode 0.770s 116.174us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.060s 316.906us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 75.400us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.650s 26.163us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.240s 201.250us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.240s 201.250us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.620s 25.171us 1 1 100.00
edn_csr_rw 0.740s 17.004us 1 1 100.00
edn_csr_aliasing 0.810s 16.953us 1 1 100.00
edn_same_csr_outstanding 0.800s 27.244us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.620s 25.171us 1 1 100.00
edn_csr_rw 0.740s 17.004us 1 1 100.00
edn_csr_aliasing 0.810s 16.953us 1 1 100.00
edn_same_csr_outstanding 0.800s 27.244us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.770s 1430.268us 1 1 100.00
edn_tl_intg_err 1.090s 388.968us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.770s 31.012us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.720s 112.997us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.770s 1430.268us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.770s 1430.268us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.770s 1430.268us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.770s 1430.268us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.720s 112.997us 1 1 100.00
edn_sec_cm 7.770s 1430.268us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.720s 112.997us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.090s 388.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 40.850s 11867.878us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_csr_mem_rw_with_rand_reset 58021103641923136725157313753140031596617050651453469737989389127242045772206 95
UVM_INFO @ 10004466622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---