Simulation Results: entropy_src/rng_4bits

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 75.49 %
  • code
  • 88.40 %
  • assert
  • 84.89 %
  • func
  • 53.17 %
  • block
  • 94.45 %
  • line
  • 97.16 %
  • branch
  • 86.58 %
  • toggle
  • 76.10 %
  • FSM
  • 93.75 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 1.000s 179.515us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 90.012us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 0.000s 38.267us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 10.000s 824.551us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 43.303us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 68.917us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 0.000s 38.267us 1 1 100.00
entropy_src_csr_aliasing 2.000s 43.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 1.000s 179.515us 1 1 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
entropy_src_fw_ov 96.000s 13097.746us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 96.000s 13097.746us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 77.000s 14219.019us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
entropy_src_intr 2.000s 90.320us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
entropy_src_functional_alerts 2.000s 697.385us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 79.000s 14540.955us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 1.000s 64.898us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 5.000s 125.446us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 15.473us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 19.896us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 29.928us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 29.928us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 90.012us 1 1 100.00
entropy_src_csr_rw 0.000s 38.267us 1 1 100.00
entropy_src_csr_aliasing 2.000s 43.303us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 1117.446us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 90.012us 1 1 100.00
entropy_src_csr_rw 0.000s 38.267us 1 1 100.00
entropy_src_csr_aliasing 2.000s 43.303us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 1117.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 319.097us 1 1 100.00
entropy_src_tl_intg_err 2.000s 68.555us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
entropy_src_cfg_regwen 1.000s 37.148us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
entropy_src_fw_ov 96.000s 13097.746us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 1.000s 64.898us 1 1 100.00
entropy_src_sec_cm 2.000s 319.097us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 1.000s 64.898us 1 1 100.00
entropy_src_sec_cm 2.000s 319.097us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 103.000s 14028.063us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 1.000s 64.898us 1 1 100.00
entropy_src_sec_cm 2.000s 319.097us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 1.000s 64.898us 1 1 100.00
entropy_src_sec_cm 2.000s 319.097us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 1.000s 64.898us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 2.000s 697.385us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 68.555us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 99.000s 13197.591us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 1.000s 22.029us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.alert_test 1 test run
entropy_src_stress_all_with_rand_reset 73086121412855355041322247822392893003382541839738363034673422450124854730483 125
UVM_INFO @ 22028568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---