Simulation Results: hmac

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.77 %
  • code
  • 86.61 %
  • assert
  • 97.38 %
  • func
  • 43.32 %
  • line
  • 99.49 %
  • branch
  • 98.37 %
  • cond
  • 94.90 %
  • toggle
  • 46.17 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.670s 111.608us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.590s 48.743us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.730s 54.593us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.920s 591.758us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.200s 1380.599us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.220s 399.320us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.730s 54.593us 1 1 100.00
hmac_csr_aliasing 1.200s 1380.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 46.050s 1804.785us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 21.820s 2473.829us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.060s 437.611us 1 1 100.00
hmac_test_sha384_vectors 17.830s 748.389us 1 1 100.00
hmac_test_sha512_vectors 368.370s 19166.813us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 1263.106us 1 1 100.00
hmac_test_hmac384_vectors 8.240s 1398.887us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 928.567us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.350s 3668.988us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 907.460s 43592.846us 1 1 100.00
error 1 1 100.00
hmac_error 37.770s 11072.335us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 102.810s 8411.547us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.670s 111.608us 1 1 100.00
hmac_long_msg 46.050s 1804.785us 1 1 100.00
hmac_back_pressure 21.820s 2473.829us 1 1 100.00
hmac_datapath_stress 907.460s 43592.846us 1 1 100.00
hmac_burst_wr 7.350s 3668.988us 1 1 100.00
hmac_stress_all 465.810s 27405.948us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.670s 111.608us 1 1 100.00
hmac_long_msg 46.050s 1804.785us 1 1 100.00
hmac_back_pressure 21.820s 2473.829us 1 1 100.00
hmac_datapath_stress 907.460s 43592.846us 1 1 100.00
hmac_wipe_secret 102.810s 8411.547us 1 1 100.00
hmac_test_sha256_vectors 7.060s 437.611us 1 1 100.00
hmac_test_sha384_vectors 17.830s 748.389us 1 1 100.00
hmac_test_sha512_vectors 368.370s 19166.813us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 1263.106us 1 1 100.00
hmac_test_hmac384_vectors 8.240s 1398.887us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 928.567us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.670s 111.608us 1 1 100.00
hmac_long_msg 46.050s 1804.785us 1 1 100.00
hmac_back_pressure 21.820s 2473.829us 1 1 100.00
hmac_datapath_stress 907.460s 43592.846us 1 1 100.00
hmac_burst_wr 7.350s 3668.988us 1 1 100.00
hmac_error 37.770s 11072.335us 1 1 100.00
hmac_wipe_secret 102.810s 8411.547us 1 1 100.00
hmac_test_sha256_vectors 7.060s 437.611us 1 1 100.00
hmac_test_sha384_vectors 17.830s 748.389us 1 1 100.00
hmac_test_sha512_vectors 368.370s 19166.813us 1 1 100.00
hmac_test_hmac256_vectors 7.540s 1263.106us 1 1 100.00
hmac_test_hmac384_vectors 8.240s 1398.887us 1 1 100.00
hmac_test_hmac512_vectors 9.990s 928.567us 1 1 100.00
hmac_stress_all 465.810s 27405.948us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 465.810s 27405.948us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.540s 208.592us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.540s 16.255us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.280s 300.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.280s 300.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.590s 48.743us 1 1 100.00
hmac_csr_rw 0.730s 54.593us 1 1 100.00
hmac_csr_aliasing 1.200s 1380.599us 1 1 100.00
hmac_same_csr_outstanding 1.300s 388.373us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.590s 48.743us 1 1 100.00
hmac_csr_rw 0.730s 54.593us 1 1 100.00
hmac_csr_aliasing 1.200s 1380.599us 1 1 100.00
hmac_same_csr_outstanding 1.300s 388.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.830s 420.354us 1 1 100.00
hmac_tl_intg_err 2.170s 1175.048us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.170s 1175.048us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.670s 111.608us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.230s 135.093us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 47.580s 6957.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.760s 543.060us 1 1 100.00