Simulation Results: i2c

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.64 %
  • code
  • 79.13 %
  • assert
  • 97.46 %
  • func
  • 80.34 %
  • line
  • 96.82 %
  • branch
  • 92.83 %
  • cond
  • 85.68 %
  • toggle
  • 73.87 %
  • FSM
  • 46.43 %
Validation stages
V1
100.00%
V2
92.68%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 15.430s 6692.171us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 12.670s 761.320us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.600s 17.038us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.630s 45.076us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 1.930s 297.208us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 0.570s 39.103us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.740s 309.578us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.630s 45.076us 1 1 100.00
i2c_csr_aliasing 0.570s 39.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 0.950s 382.331us 1 1 100.00
host_stress_all 0 1 0.00
i2c_host_stress_all 35.020s 2656.671us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 8.010s 6632.845us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.610s 43.742us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 31.090s 5224.411us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 42.510s 1434.042us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.050s 303.040us 1 1 100.00
i2c_host_fifo_fmt_empty 10.780s 1855.044us 1 1 100.00
i2c_host_fifo_reset_rx 2.600s 383.939us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 96.490s 3342.477us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.060s 4832.664us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 0.550s 397.080us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.650s 577.991us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 725.820s 59334.876us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 1.840s 456.701us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 21.570s 1354.584us 1 1 100.00
i2c_target_intr_smoke 3.010s 3684.747us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.960s 382.364us 1 1 100.00
i2c_target_fifo_reset_tx 0.990s 230.741us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 207.360s 56999.195us 1 1 100.00
i2c_target_stress_rd 21.570s 1354.584us 1 1 100.00
i2c_target_intr_stress_wr 5.980s 11482.920us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.930s 1615.529us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 73.350s 3698.825us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.200s 3235.252us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 3.820s 10067.113us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 0.990s 831.866us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.000s 499.845us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 8.010s 6632.845us 1 1 100.00
i2c_host_perf_precise 6.790s 381.996us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.060s 4832.664us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.820s 437.391us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.790s 1108.380us 1 1 100.00
i2c_target_nack_acqfull_addr 1.310s 6720.783us 1 1 100.00
i2c_target_nack_txstretch 1.200s 514.821us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.060s 2211.735us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.510s 999.007us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.610s 95.554us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.540s 25.373us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 0.880s 27.400us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 0.880s 27.400us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.600s 17.038us 1 1 100.00
i2c_csr_rw 0.630s 45.076us 1 1 100.00
i2c_csr_aliasing 0.570s 39.103us 1 1 100.00
i2c_same_csr_outstanding 0.610s 39.302us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.600s 17.038us 1 1 100.00
i2c_csr_rw 0.630s 45.076us 1 1 100.00
i2c_csr_aliasing 0.570s 39.103us 1 1 100.00
i2c_same_csr_outstanding 0.610s 39.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.780s 851.013us 1 1 100.00
i2c_sec_cm 0.720s 134.782us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.780s 851.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 8.430s 1895.394us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.990s 529.987us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 0.760s 186.114us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_stress_all 92512960410285807855444027254162419105084309278873059943162254039310627557314 111
UVM_INFO @ 2656670818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 79380370137275519383070186864693503257849847697653804655391629832233189315296 91
UVM_INFO @ 186113928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 6267825072016542900037794375592480419579826940961016961144956789996710901424 90
UVM_INFO @ 577991168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 17452156117298484223910616865273317065224525995114170486590985801578896021200 84
UVM_INFO @ 529986590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 44243763813184705103538440668365784947528007321251511007630468115340005082901 85
UVM_INFO @ 10067113322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 50272920566435205186142551128986924065863055406064367768460896855054593943144 115
UVM_INFO @ 1895393702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---