Simulation Results: keymgr_dpe/earlgrey

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.09 %
  • code
  • 82.50 %
  • assert
  • 97.67 %
  • func
  • 15.09 %
  • line
  • 97.52 %
  • branch
  • 93.58 %
  • cond
  • 86.46 %
  • toggle
  • 59.24 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 10.050s 812.196us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 0.740s 17.614us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.870s 44.049us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 7.070s 908.685us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 0.850s 30.156us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.310s 120.613us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 0.870s 44.049us 1 1 100.00
keymgr_dpe_csr_aliasing 0.850s 30.156us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.560s 14.356us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 0.630s 16.360us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 1.550s 35.707us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 1.550s 35.707us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.740s 17.614us 1 1 100.00
keymgr_dpe_csr_rw 0.870s 44.049us 1 1 100.00
keymgr_dpe_csr_aliasing 0.850s 30.156us 1 1 100.00
keymgr_dpe_same_csr_outstanding 0.980s 51.425us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.740s 17.614us 1 1 100.00
keymgr_dpe_csr_rw 0.870s 44.049us 1 1 100.00
keymgr_dpe_csr_aliasing 0.850s 30.156us 1 1 100.00
keymgr_dpe_same_csr_outstanding 0.980s 51.425us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 6.630s 888.858us 1 1 100.00
keymgr_dpe_tl_intg_err 2.510s 151.075us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.570s 6.084us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.570s 6.084us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.570s 6.084us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.570s 6.084us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 2.660s 456.421us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 6.630s 888.858us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 6.630s 888.858us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 2 test runs
keymgr_dpe_shadow_reg_errors 82227909473526922482417241069691300138495744538838088313758653202442823092446 83
UVM_ERROR @ 6084111 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 6084111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_shadow_reg_errors_with_csr_rw 26683968605647700091043315080093959243817615223435768568008964981338076390246 83
UVM_ERROR @ 456420978 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 456420978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---