Simulation Results: lc_ctrl/volatile_unlock_disabled

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.88 %
  • code
  • 84.40 %
  • assert
  • 94.69 %
  • func
  • 93.55 %
  • line
  • 97.24 %
  • branch
  • 93.90 %
  • cond
  • 79.45 %
  • toggle
  • 87.85 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.640s 25.020us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.720s 20.864us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.670s 13.455us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.900s 34.499us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.650s 50.477us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.810s 271.445us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.670s 13.455us 1 1 100.00
lc_ctrl_csr_aliasing 0.650s 50.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.200s 230.117us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.650s 412.762us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.610s 40.588us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.080s 50.103us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.320s 283.200us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_prog_failure 1.080s 50.103us 1 1 100.00
lc_ctrl_errors 4.320s 283.200us 1 1 100.00
lc_ctrl_security_escalation 3.480s 1167.772us 1 1 100.00
lc_ctrl_jtag_state_failure 25.780s 3906.215us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.700s 381.996us 1 1 100.00
lc_ctrl_jtag_errors 10.190s 1186.581us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.090s 213.669us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.240s 288.440us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.700s 381.996us 1 1 100.00
lc_ctrl_jtag_errors 10.190s 1186.581us 1 1 100.00
lc_ctrl_jtag_access 3.200s 928.951us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.340s 3874.883us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.360s 370.370us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.870s 130.937us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 2.780s 406.009us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.190s 88.793us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.830s 111.159us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.250s 78.978us 1 1 100.00
lc_ctrl_jtag_alert_test 0.760s 71.345us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.380s 5923.670us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.540s 11.985us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 47.530s 32830.059us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.710s 96.568us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.020s 451.578us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.020s 451.578us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.720s 20.864us 1 1 100.00
lc_ctrl_csr_rw 0.670s 13.455us 1 1 100.00
lc_ctrl_csr_aliasing 0.650s 50.477us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.960s 84.272us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.720s 20.864us 1 1 100.00
lc_ctrl_csr_rw 0.670s 13.455us 1 1 100.00
lc_ctrl_csr_aliasing 0.650s 50.477us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.960s 84.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
lc_ctrl_tl_intg_err 0.820s 150.632us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 0.820s 150.632us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.650s 412.762us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.620s 816.543us 1 1 100.00
lc_ctrl_sec_cm 4.760s 344.970us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.480s 1167.772us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.200s 230.117us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.240s 288.440us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.760s 308.662us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.760s 308.662us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.680s 1620.866us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.190s 236.704us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.190s 236.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 23.720s 4564.089us 1 1 100.00