Simulation Results: lc_ctrl/volatile_unlock_enabled

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 89.30 %
  • code
  • 81.86 %
  • assert
  • 94.83 %
  • func
  • 91.22 %
  • line
  • 96.95 %
  • branch
  • 93.00 %
  • cond
  • 78.66 %
  • toggle
  • 78.08 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.970s 247.393us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.570s 35.589us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.570s 24.114us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.250s 102.816us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.670s 36.640us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.660s 50.019us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.570s 24.114us 1 1 100.00
lc_ctrl_csr_aliasing 0.670s 36.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.580s 70.443us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.870s 341.162us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.550s 14.859us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 0.790s 87.211us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.660s 779.506us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_prog_failure 0.790s 87.211us 1 1 100.00
lc_ctrl_errors 3.660s 779.506us 1 1 100.00
lc_ctrl_security_escalation 3.790s 389.340us 1 1 100.00
lc_ctrl_jtag_state_failure 5.560s 807.833us 0 1 0.00
lc_ctrl_jtag_prog_failure 1.950s 723.847us 1 1 100.00
lc_ctrl_jtag_errors 6.230s 751.326us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 0.940s 135.127us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.460s 549.187us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.950s 723.847us 1 1 100.00
lc_ctrl_jtag_errors 6.230s 751.326us 0 1 0.00
lc_ctrl_jtag_access 1.090s 104.583us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.060s 697.973us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 0.860s 159.140us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.680s 88.507us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.200s 671.419us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.360s 204.912us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.780s 21.109us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.290s 123.274us 1 1 100.00
lc_ctrl_jtag_alert_test 0.600s 44.702us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.300s 303.955us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.550s 45.899us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 5.510s 636.557us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.740s 24.243us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.320s 654.717us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.320s 654.717us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.570s 35.589us 1 1 100.00
lc_ctrl_csr_rw 0.570s 24.114us 1 1 100.00
lc_ctrl_csr_aliasing 0.670s 36.640us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.730s 23.522us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.570s 35.589us 1 1 100.00
lc_ctrl_csr_rw 0.570s 24.114us 1 1 100.00
lc_ctrl_csr_aliasing 0.670s 36.640us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.730s 23.522us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
lc_ctrl_tl_intg_err 1.220s 152.468us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.220s 152.468us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.870s 341.162us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 5.750s 352.594us 1 1 100.00
lc_ctrl_sec_cm 4.550s 2213.897us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.790s 389.340us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.580s 70.443us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.460s 549.187us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 2.220s 352.562us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 2.220s 352.562us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.600s 277.453us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.980s 288.019us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.980s 288.019us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 7.820s 2369.763us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 61492983222935612887343804327921080078861532473574089094688073013702824974093 626
UVM_INFO @ 807832598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57200539088545490258640739021944549343881296570733976075403828053915111874707 2969
UVM_INFO @ 2369762730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_errors 110937545776843009025482840822894323117649416793107765818864400495615698578626 1842
UVM_INFO @ 751325817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---