Simulation Results: otp_ctrl

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 78.70 %
  • code
  • 75.28 %
  • assert
  • 92.34 %
  • func
  • 68.47 %
  • line
  • 88.17 %
  • branch
  • 81.58 %
  • cond
  • 89.24 %
  • toggle
  • 77.33 %
  • FSM
  • 40.10 %
Validation stages
V1
100.00%
V2
80.00%
V2S
44.44%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.000s 109.227us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 2.470s 260.480us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.270s 396.852us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 0.950s 49.132us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.930s 2210.199us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 0.940s 43.355us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.040s 75.002us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 0.950s 49.132us 1 1 100.00
otp_ctrl_csr_aliasing 0.940s 43.355us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 0.760s 77.072us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.000s 477.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 10.800s 1638.973us 1 1 100.00
init_fail 0 1 0.00
otp_ctrl_init_fail 2.250s 161.022us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 14.630s 1867.590us 1 1 100.00
otp_ctrl_check_fail 10.880s 2702.192us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.550s 714.348us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 5.810s 1203.833us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 5.370s 501.790us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.150s 1898.734us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 9.380s 322.578us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.730s 295.839us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 14.580s 1102.964us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 44.810s 14518.939us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 0.860s 98.253us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.140s 68.076us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.350s 2129.288us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.350s 2129.288us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.270s 396.852us 1 1 100.00
otp_ctrl_csr_rw 0.950s 49.132us 1 1 100.00
otp_ctrl_csr_aliasing 0.940s 43.355us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.550s 147.614us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.270s 396.852us 1 1 100.00
otp_ctrl_csr_rw 0.950s 49.132us 1 1 100.00
otp_ctrl_csr_aliasing 0.940s 43.355us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.550s 147.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
tl_intg_err 0 2 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
otp_ctrl_tl_intg_err 11.450s 8475.794us 0 1 0.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
otp_ctrl_tl_intg_err 11.450s 8475.794us 0 1 0.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 2.470s 260.480us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 2.470s 260.480us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
otp_ctrl_macro_errs 2.730s 295.839us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
otp_ctrl_macro_errs 2.730s 295.839us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.700s 863.610us 1 1 100.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 2.250s 161.022us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 10.880s 2702.192us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 5.810s 1203.833us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 5.810s 1203.833us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 5.810s 1203.833us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 5.810s 1203.833us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 5.810s 1203.833us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 2.470s 260.480us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 5.810s 1203.833us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 2.470s 260.480us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 8.130s 9174.443us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.550s 714.348us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 2.470s 260.480us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 2.470s 260.480us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.730s 295.839us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.480s 3541.260us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 34.210s 10688.663us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 954362327199141262916751332788581851279055819544605441299549541127140497654 8768
UVM_INFO @ 2702192253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 103703871587973060145170450404053015249342352328432596080135390122849358092296 1381
UVM_INFO @ 295839128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_macro_error does not trigger! 1 test run
otp_ctrl_init_fail 91423659347217520906450257845679224921193924846062522823500755855015961899557 2121
UVM_INFO @ 161021904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 90470902027377835265647616054411349688065517799300425039841121629283409887951 6743
UVM_INFO @ 10688663497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 1 test run
otp_ctrl_stress_all 25754806122439112293460873455277408718369469250510965897032955051841541965597 30603
UVM_INFO @ 14518938761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_check_error) did not fire in * cycles. 1 test run
otp_ctrl_sec_cm 99483128753309877070114578552116959976972022529058828772921849026523728471615 238
UVM_INFO @ 9174442961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_bus_integ_error) did not fire in * cycles. 1 test run
otp_ctrl_tl_intg_err 97564517346709922312892205259874832019031519766850880722353811864319331417766 255
UVM_INFO @ 8475793764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---