Simulation Results: pwrmgr

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 94.73 %
  • code
  • 90.07 %
  • assert
  • 97.91 %
  • func
  • 96.21 %
  • line
  • 98.93 %
  • branch
  • 95.62 %
  • cond
  • 93.78 %
  • toggle
  • 90.02 %
  • FSM
  • 72.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
81.82%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.380s 47.316us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.370s 98.455us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.370s 81.681us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.920s 674.106us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.420s 21.534us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.480s 56.113us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.370s 81.681us 1 1 100.00
pwrmgr_csr_aliasing 0.420s 21.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.440s 87.871us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.440s 87.871us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.520s 34.183us 1 1 100.00
pwrmgr_lowpower_invalid 0.420s 47.422us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.490s 62.007us 1 1 100.00
pwrmgr_reset_invalid 3600.023s 0.000us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.490s 62.007us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.780s 384.463us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.600s 392.580us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.430s 52.392us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.760s 141.564us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.400s 43.850us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 0.950s 74.602us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 0.950s 74.602us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.370s 98.455us 1 1 100.00
pwrmgr_csr_rw 0.370s 81.681us 1 1 100.00
pwrmgr_csr_aliasing 0.420s 21.534us 1 1 100.00
pwrmgr_same_csr_outstanding 0.470s 21.600us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.370s 98.455us 1 1 100.00
pwrmgr_csr_rw 0.370s 81.681us 1 1 100.00
pwrmgr_csr_aliasing 0.420s 21.534us 1 1 100.00
pwrmgr_same_csr_outstanding 0.470s 21.600us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.017s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.019s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.019s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.019s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.017s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.190s 790.194us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.780s 384.463us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.170s 1293.644us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.540s 169.346us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.370s 40.378us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.019s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.019s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.019s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.410s 49.509us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.370s 41.391us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.430s 212.725us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.370s 81.681us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.370s 81.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.450s 370.801us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.020s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
pwrmgr_reset_invalid 49036747018737887573595291038361157815917877472762395109633573343818194773600 None
pwrmgr_tl_intg_err 38276535454361512982778946808153443495219955033694002223561338956544032722245 None
pwrmgr_sec_cm 35738388706689581986856655173993289458585556629805372594749170246209944074575 None
pwrmgr_stress_all_with_rand_reset 70399393613376983704621724455717660545607040449826079920459460796786957953794 None
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 60229975259473107628677591109141981483736756811848773733780847831620167865011 85
UVM_ERROR @ 370801184 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 370801184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---