Simulation Results: rom_ctrl/192kb

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 88.00 %
  • code
  • 87.72 %
  • assert
  • 97.39 %
  • func
  • 78.90 %
  • line
  • 97.76 %
  • branch
  • 97.83 %
  • cond
  • 94.96 %
  • toggle
  • 94.73 %
  • FSM
  • 53.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.080s 1054.505us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.230s 56.204us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.330s 107.286us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.900s 119.552us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.240s 52.176us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.680s 66.519us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.330s 107.286us 1 1 100.00
rom_ctrl_csr_aliasing 5.240s 52.176us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.480s 58.082us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.630s 48.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.460s 2.272us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 47.320s 4014.450us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.710s 1035.208us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.360s 81.026us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.520s 342.343us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.520s 342.343us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.230s 56.204us 1 1 100.00
rom_ctrl_csr_rw 4.330s 107.286us 1 1 100.00
rom_ctrl_csr_aliasing 5.240s 52.176us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.960s 69.592us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 12.230s 56.204us 1 1 100.00
rom_ctrl_csr_rw 4.330s 107.286us 1 1 100.00
rom_ctrl_csr_aliasing 5.240s 52.176us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.960s 69.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.930s 176.042us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 773.780s 783.360us 1 1 100.00
rom_ctrl_tl_intg_err 82.610s 222.886us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 773.780s 783.360us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 773.780s 783.360us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 773.780s 783.360us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 773.780s 783.360us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.080s 1054.505us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.080s 1054.505us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.080s 1054.505us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 82.610s 222.886us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
rom_ctrl_kmac_err_chk 12.710s 1035.208us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 105.210s 12293.442us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.930s 176.042us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 773.780s 783.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 6.340s 1432.430us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 36020741877667259257767675527138955253812536415398913033788328043973729903340 85
UVM_INFO @ 2272320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
rom_ctrl_corrupt_sig_fatal_chk 82205168812123978060550619913501679367606086684990778685444401152944000937344 96
UVM_INFO @ 12293442160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rom_ctrl_stress_all_with_rand_reset 98278519507770763361730261390306607039103340156152009699892207699687840868280 86
UVM_INFO @ 1432430385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---