Simulation Results: rstmgr

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 99.25 %
  • assert
  • 98.26 %
  • func
  • 96.77 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.26 %
  • toggle
  • 99.41 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 0.940s 265.538us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.440s 95.575us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.500s 75.664us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.630s 1448.286us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.510s 85.663us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.530s 115.734us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.500s 75.664us 1 1 100.00
rstmgr_csr_aliasing 0.510s 85.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.550s 231.107us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.750s 655.652us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.670s 151.027us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.460s 2239.339us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.460s 2239.339us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.460s 2239.339us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.460s 2239.339us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 2.800s 1071.296us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.550s 92.564us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.240s 167.947us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.240s 167.947us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.440s 95.575us 1 1 100.00
rstmgr_csr_rw 0.500s 75.664us 1 1 100.00
rstmgr_csr_aliasing 0.510s 85.663us 1 1 100.00
rstmgr_same_csr_outstanding 0.750s 130.316us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.440s 95.575us 1 1 100.00
rstmgr_csr_rw 0.500s 75.664us 1 1 100.00
rstmgr_csr_aliasing 0.510s 85.663us 1 1 100.00
rstmgr_same_csr_outstanding 0.750s 130.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 14.690s 16873.047us 1 1 100.00
rstmgr_tl_intg_err 1.200s 511.448us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 14.690s 16873.047us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 14.690s 16873.047us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.200s 511.448us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.570s 117.536us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.800s 2544.719us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.730s 302.410us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 14.690s 16873.047us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.500s 75.664us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.500s 75.664us 1 1 100.00