Simulation Results: rv_timer

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.50 %
  • code
  • 94.66 %
  • assert
  • 97.77 %
  • func
  • 97.06 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.340s 95.871us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.340s 22.059us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.340s 22.562us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.500s 617.134us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.380s 57.074us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.500s 115.944us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.340s 22.562us 1 1 100.00
rv_timer_csr_aliasing 0.380s 57.074us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.380s 2834.145us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 0.590s 455.264us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 184.300s 446341.676us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 184.300s 446341.676us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.270s 4772.670us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.350s 47.953us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.300s 52.221us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.880s 41.084us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.880s 41.084us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.340s 22.059us 1 1 100.00
rv_timer_csr_rw 0.340s 22.562us 1 1 100.00
rv_timer_csr_aliasing 0.380s 57.074us 1 1 100.00
rv_timer_same_csr_outstanding 0.420s 36.348us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.340s 22.059us 1 1 100.00
rv_timer_csr_rw 0.340s 22.562us 1 1 100.00
rv_timer_csr_aliasing 0.380s 57.074us 1 1 100.00
rv_timer_same_csr_outstanding 0.420s 36.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.420s 1102.670us 1 1 100.00
rv_timer_tl_intg_err 0.530s 163.555us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.530s 163.555us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.570s 189.390us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.320s 82.101us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 10.360s 1930.954us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 92034520708763217551190696777561825389330093428488827500669533533094423712813 84
UVM_INFO @ 189390120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:342) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 114485227530951563843739672307142056308462788263004795940124782626757603696885 81
UVM_INFO @ 82101161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---