Simulation Results: spi_device/1r1w

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.43 %
  • code
  • 91.36 %
  • assert
  • 95.40 %
  • func
  • 69.54 %
  • line
  • 98.88 %
  • branch
  • 98.18 %
  • cond
  • 96.10 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 58.130s 11304.036us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.670s 191.023us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 0.510s 51.444us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 24.100s 3006.110us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 0.790s 134.954us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.860s 630.127us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 0.510s 51.444us 1 1 100.00
spi_device_csr_aliasing 0.790s 134.954us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.330s 10.885us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 0.850s 241.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.420s 29.269us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.380s 2.907us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.360s 3.635us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.590s 80.341us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.590s 80.341us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.470s 17617.841us 1 1 100.00
spi_device_tpm_sts_read 0.420s 25.067us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 12.500s 10371.429us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.070s 1700.991us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.380s 8672.010us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.380s 8672.010us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 1.400s 692.140us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 1.400s 692.140us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 1.400s 692.140us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 1.400s 692.140us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 1.400s 692.140us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.250s 1166.908us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.550s 309.347us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.550s 309.347us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.550s 309.347us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 1.580s 242.985us 1 1 100.00
spi_device_read_buffer_direct 1.730s 1346.103us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.550s 309.347us 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 22.150s 14773.905us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 0.880s 143.418us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 0.880s 143.418us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 1.830s 547.539us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 58.130s 11304.036us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 26.070s 7098.853us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.900s 116.171us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.360s 15.369us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.380s 11.588us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.740s 223.063us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.740s 223.063us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.670s 191.023us 1 1 100.00
spi_device_csr_rw 0.510s 51.444us 1 1 100.00
spi_device_csr_aliasing 0.790s 134.954us 1 1 100.00
spi_device_same_csr_outstanding 2.420s 786.490us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.670s 191.023us 1 1 100.00
spi_device_csr_rw 0.510s 51.444us 1 1 100.00
spi_device_csr_aliasing 0.790s 134.954us 1 1 100.00
spi_device_same_csr_outstanding 2.420s 786.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.530s 394.431us 1 1 100.00
spi_device_tl_intg_err 5.410s 200.426us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.410s 200.426us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 34485373617620267295744997540519541799291515203491063938280895223386298864822 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2416895 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2416895 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[995])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 110708628111831410001394260673709195129867607451332587605285293825096632867636 76
UVM_ERROR @ 1150314 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x11c [100011100] vs 0x0 [0])
UVM_ERROR @ 1171314 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x68 [1101000] vs 0x0 [0])
UVM_ERROR @ 1264314 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e8 [1011101000] vs 0x0 [0])
UVM_ERROR @ 1316314 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2aa [1010101010] vs 0x0 [0])