Simulation Results: spi_host

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.23 %
  • code
  • 91.30 %
  • assert
  • 94.14 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 12.000s 1476.614us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 30.234us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 0.000s 39.273us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 830.062us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 3.000s 28.398us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 0.000s 80.553us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 0.000s 39.273us 1 1 100.00
spi_host_csr_aliasing 3.000s 28.398us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 0.000s 24.751us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 0.000s 33.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 3.000s 23.121us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 193.149us 1 1 100.00
spi_host_error_cmd 3.000s 23.283us 1 1 100.00
spi_host_event 22.000s 4756.415us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 117.889us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 117.889us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 117.889us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 72.000s 7771.070us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 4.000s 31.503us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 3.000s 48.220us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 117.889us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 117.889us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 12.000s 1476.614us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 12.000s 1476.614us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 4.000s 127.984us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 233.603us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 32.000s 1524.102us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 4.000s 149.596us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 193.149us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 3.000s 42.459us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 0.000s 20.067us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 0.000s 41.439us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 0.000s 41.439us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.234us 1 1 100.00
spi_host_csr_rw 0.000s 39.273us 1 1 100.00
spi_host_csr_aliasing 3.000s 28.398us 1 1 100.00
spi_host_same_csr_outstanding 0.000s 28.993us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.234us 1 1 100.00
spi_host_csr_rw 0.000s 39.273us 1 1 100.00
spi_host_csr_aliasing 3.000s 28.398us 1 1 100.00
spi_host_same_csr_outstanding 0.000s 28.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 450.150us 1 1 100.00
spi_host_sec_cm 3.000s 42.353us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 450.150us 1 1 100.00