Simulation Results: sram_ctrl/main

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.25 %
  • code
  • 94.32 %
  • assert
  • 97.83 %
  • func
  • 93.60 %
  • block
  • 93.47 %
  • line
  • 94.53 %
  • branch
  • 90.91 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 2659.749us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 22.649us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 39.681us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 57.704us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 62.763us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1432.454us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 39.681us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 62.763us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 198.000s 46320.243us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 99.000s 10830.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 3.000s 1097.847us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 117.000s 9423.735us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 138.000s 31611.429us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 33.000s 9979.598us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 11.000s 4621.204us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 27.000s 8478.940us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1407.346us 1 1 100.00
sram_ctrl_partial_access_b2b 87.000s 49893.434us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 685.955us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 1815.913us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 1370.103us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 4321.932us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1476.810us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 3.000s 2659.749us 1 1 100.00
sram_ctrl_partial_access 3.000s 1407.346us 1 1 100.00
sram_ctrl_access_during_key_req 33.000s 9979.598us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 152.000s 22728.761us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.168us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 137.762us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 137.762us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 22.649us 1 1 100.00
sram_ctrl_csr_rw 1.000s 39.681us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 62.763us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 21.526us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 22.649us 1 1 100.00
sram_ctrl_csr_rw 1.000s 39.681us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 62.763us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 21.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 28171.699us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 2142.751us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1011.094us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 2142.751us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1011.094us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 4321.932us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 4321.932us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 39.681us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 27.000s 8478.940us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 8478.940us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 8478.940us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 11.000s 4621.204us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 28171.699us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 2659.749us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 2659.749us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 27.000s 8478.940us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 2142.751us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 11.000s 4621.204us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 2142.751us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 2142.751us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 2659.749us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 2142.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 26.000s 4467.784us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 35208104834704658215331588444847588566451432016936589385692604222101290770256 None
sram_ctrl_mubi_enc_err 80269424242146675094703959527478213550526214470117489099060019164105708385736 None