Simulation Results: sram_ctrl/ret

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.74 %
  • code
  • 81.75 %
  • assert
  • 97.26 %
  • func
  • 93.20 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 76.441us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.000s 20.503us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.000s 34.376us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 262.983us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.000s 20.130us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 33.381us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.000s 34.376us 1 1 100.00
sram_ctrl_csr_aliasing 0.000s 20.130us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.000s 425.155us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 201.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 1138.991us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 173.000s 17455.919us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 3006.455us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 1035.968us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 3293.100us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 4.000s 514.408us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 30.072us 1 1 100.00
sram_ctrl_partial_access_b2b 182.000s 17525.578us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 49.605us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 42.885us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 138.830us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 2.000s 87.957us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 27.336us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 1.000s 76.441us 1 1 100.00
sram_ctrl_partial_access 1.000s 30.072us 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 1035.968us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 21.000s 1207.531us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 47.841us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.000s 124.053us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.000s 124.053us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.000s 20.503us 1 1 100.00
sram_ctrl_csr_rw 0.000s 34.376us 1 1 100.00
sram_ctrl_csr_aliasing 0.000s 20.130us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.000s 23.392us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.000s 20.503us 1 1 100.00
sram_ctrl_csr_rw 0.000s 34.376us 1 1 100.00
sram_ctrl_csr_aliasing 0.000s 20.130us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.000s 23.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.000s 428.933us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 4270.399us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 324.181us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 4270.399us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 324.181us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 2.000s 87.957us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 2.000s 87.957us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.000s 34.376us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 4.000s 514.408us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 514.408us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 4.000s 514.408us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 3293.100us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.000s 428.933us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 76.441us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 76.441us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 4.000s 514.408us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 4270.399us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 3293.100us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 4270.399us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 4270.399us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 76.441us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 4270.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 18.000s 5514.537us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 103114251414738193760827953811487101560776853538766356589384062933314035304579 None
sram_ctrl_mubi_enc_err 103052476111722495101545530162169098004036440483576386016820858853047219331982 None