Simulation Results: sysrst_ctrl

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.32 %
  • code
  • 92.66 %
  • assert
  • 94.51 %
  • func
  • 65.79 %
  • line
  • 97.26 %
  • branch
  • 97.40 %
  • cond
  • 95.13 %
  • toggle
  • 99.77 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.620s 2109.461us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 0.990s 2472.690us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.740s 2406.715us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 3.070s 2333.193us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 7.040s 6015.623us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.710s 2054.064us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 17.480s 39156.698us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 1.150s 2302.714us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 0.740s 2189.739us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.710s 2054.064us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.150s 2302.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 41.800s 86473.300us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 23.080s 88971.980us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 0.750s 3513.276us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.870s 3593.727us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.130s 2525.559us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 0.790s 2233.508us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.240s 3511.939us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.050s 2638.214us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 0.950s 2492.669us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 24.820s 41340.290us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 17.460s 13068.633us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 0.910s 2029.079us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 0.780s 2033.255us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.430s 2312.359us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.430s 2312.359us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.040s 6015.623us 1 1 100.00
sysrst_ctrl_csr_rw 2.710s 2054.064us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.150s 2302.714us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.300s 9228.364us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.040s 6015.623us 1 1 100.00
sysrst_ctrl_csr_rw 2.710s 2054.064us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.150s 2302.714us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.300s 9228.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 1.890s 22351.958us 1 1 100.00
sysrst_ctrl_tl_intg_err 10.420s 43316.596us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 10.420s 43316.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 2.180s 27745.756us 1 1 100.00