Simulation Results: uart

 
09/09/2026 17:07:42 DVSim: v1.52.2 sha: 629146e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 83.17 %
  • code
  • 91.68 %
  • assert
  • 98.27 %
  • func
  • 59.57 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.45 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 12.600s 5844.558us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.310s 12.247us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.310s 11.890us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 0.720s 50.467us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.340s 46.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.490s 74.862us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.310s 11.890us 1 1 100.00
uart_csr_aliasing 0.340s 46.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 20.230s 32202.368us 1 1 100.00
parity 2 2 100.00
uart_smoke 12.600s 5844.558us 1 1 100.00
uart_tx_rx 20.230s 32202.368us 1 1 100.00
parity_error 2 2 100.00
uart_intr 1.550s 14547.397us 1 1 100.00
uart_rx_parity_err 10.980s 66244.082us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 20.230s 32202.368us 1 1 100.00
uart_intr 1.550s 14547.397us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 69.350s 101579.542us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 28.910s 36154.284us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 22.820s 117251.707us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 1.550s 14547.397us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 1.550s 14547.397us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 1.550s 14547.397us 1 1 100.00
perf 1 1 100.00
uart_perf 34.230s 19727.163us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.340s 2388.617us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.340s 2388.617us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.680s 2460.820us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.240s 2034.743us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 6.870s 6350.232us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.020s 4969.929us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 250.310s 138874.801us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 23.110s 134521.461us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.310s 45.673us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.320s 52.442us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 0.860s 235.978us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 0.860s 235.978us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.310s 12.247us 1 1 100.00
uart_csr_rw 0.310s 11.890us 1 1 100.00
uart_csr_aliasing 0.340s 46.625us 1 1 100.00
uart_same_csr_outstanding 0.370s 28.767us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.310s 12.247us 1 1 100.00
uart_csr_rw 0.310s 11.890us 1 1 100.00
uart_csr_aliasing 0.340s 46.625us 1 1 100.00
uart_same_csr_outstanding 0.370s 28.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.480s 2076.966us 1 1 100.00
uart_tl_intg_err 0.460s 93.499us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.460s 93.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 24.470s 14246.548us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 55559269021061884299235155331366974103462260516976294351195666160005946968592 80
UVM_ERROR @ 915099591 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 915099591 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 1062859591 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1062859591 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1