Simulation Results: adc_ctrl

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.96 %
  • code
  • 97.36 %
  • assert
  • 96.92 %
  • func
  • 18.59 %
  • line
  • 99.02 %
  • branch
  • 98.45 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.650s 5837.885us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.850s 1352.753us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.850s 328.742us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 41.720s 24975.537us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.270s 622.232us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.730s 617.011us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.850s 328.742us 1 1 100.00
adc_ctrl_csr_aliasing 1.270s 622.232us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 15.920s 52855.001us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 20.830s 54941.778us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 10.150s 34921.714us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 19.630s 36149.340us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 42.440s 69929.774us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 17.930s 68925.978us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 76.660s 66393.334us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.370s 1463.906us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.500s 5046.951us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 56.820s 43173.438us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 62.560s 83421.046us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 16.930s 61734.807us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.640s 340.583us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.570s 644.109us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.210s 322.145us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.210s 322.145us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.850s 1352.753us 1 1 100.00
adc_ctrl_csr_rw 0.850s 328.742us 1 1 100.00
adc_ctrl_csr_aliasing 1.270s 622.232us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.630s 2563.034us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.850s 1352.753us 1 1 100.00
adc_ctrl_csr_rw 0.850s 328.742us 1 1 100.00
adc_ctrl_csr_aliasing 1.270s 622.232us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.630s 2563.034us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.790s 7726.346us 1 1 100.00
adc_ctrl_tl_intg_err 1.330s 6393.842us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 1.330s 6393.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 4.190s 4386.297us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
adc_ctrl_clock_gating 42154051952026561659046278020131504396390087544621361873502217690942760500735 392
UVM_INFO @ 1463906323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---