Simulation Results: aes/masked

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.46 %
  • code
  • 94.12 %
  • assert
  • 98.23 %
  • func
  • 73.04 %
  • block
  • 94.22 %
  • line
  • 95.73 %
  • branch
  • 87.20 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 237.443us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 91.656us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 83.482us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 60.446us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 894.070us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 78.740us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 120.661us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 60.446us 1 1 100.00
aes_csr_aliasing 1.000s 78.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 91.656us 1 1 100.00
aes_config_error 2.000s 110.432us 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 91.656us 1 1 100.00
aes_config_error 2.000s 110.432us 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 158.245us 1 1 100.00
aes_b2b 6.000s 610.047us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 91.656us 1 1 100.00
aes_config_error 2.000s 110.432us 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
aes_alert_reset 1.000s 82.215us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 85.820us 1 1 100.00
aes_config_error 2.000s 110.432us 1 1 100.00
aes_alert_reset 1.000s 82.215us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 1.000s 291.170us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 2760.424us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 1.000s 82.215us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 158.245us 1 1 100.00
aes_sideload 3.000s 261.075us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 318.377us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 16.000s 2502.552us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 54.098us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 95.990us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 95.990us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 83.482us 1 1 100.00
aes_csr_rw 1.000s 60.446us 1 1 100.00
aes_csr_aliasing 1.000s 78.740us 1 1 100.00
aes_same_csr_outstanding 1.000s 179.542us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 83.482us 1 1 100.00
aes_csr_rw 1.000s 60.446us 1 1 100.00
aes_csr_aliasing 1.000s 78.740us 1 1 100.00
aes_same_csr_outstanding 1.000s 179.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 580.134us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_cipher_fi 15.000s 10010.784us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 286.818us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 286.818us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 286.818us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 286.818us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 1.000s 244.552us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 2099.385us 1 1 100.00
aes_tl_intg_err 1.000s 256.425us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 256.425us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 1.000s 82.215us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 286.818us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 286.818us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 91.656us 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
aes_alert_reset 1.000s 82.215us 1 1 100.00
aes_core_fi 2.000s 131.252us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 110.432us 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
aes_core_fi 2.000s 131.252us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 286.818us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 72.704us 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 158.245us 1 1 100.00
aes_sideload 3.000s 261.075us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 72.704us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 72.704us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 72.704us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 72.704us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 72.704us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 158.245us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 653.780us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_cipher_fi 15.000s 10010.784us 0 1 0.00
aes_ctr_fi 1.000s 68.718us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 653.780us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_cipher_fi 15.000s 10010.784us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 15.000s 10010.784us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 653.780us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_ctr_fi 1.000s 68.718us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 653.780us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_cipher_fi 15.000s 10010.784us 0 1 0.00
aes_ctr_fi 1.000s 68.718us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 1.000s 82.215us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_cipher_fi 15.000s 10010.784us 0 1 0.00
aes_ctr_fi 1.000s 68.718us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_cipher_fi 15.000s 10010.784us 0 1 0.00
aes_ctr_fi 1.000s 68.718us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_ctr_fi 1.000s 68.718us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 653.780us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 653.780us 0 1 0.00
aes_control_fi 1.000s 115.079us 1 1 100.00
aes_cipher_fi 15.000s 10010.784us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 38.000s 1769.870us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 20357832550222472625184111158015433782340055487811867721333840284405238257280 12782
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 4813590962675148492402793798249096059783063991104774089506697890392378247531 148
UVM_INFO @ 10010784165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 61861081785046662996181699684015784838967806826634734619493249752385176267846 1011
UVM_INFO @ 1769869716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---