| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
93.75% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 1.000s | 92.486us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| aes_smoke | 1.000s | 174.484us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 100.148us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aes_csr_rw | 1.000s | 59.306us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 4.000s | 2612.488us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 1.000s | 61.423us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 1.000s | 97.967us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aes_csr_rw | 1.000s | 59.306us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 1.000s | 61.423us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 3 | 3 | 100.00 | |||
| aes_smoke | 1.000s | 174.484us | 1 | 1 | 100.00 | |
| aes_config_error | 1.000s | 304.862us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| key_length | 3 | 3 | 100.00 | |||
| aes_smoke | 1.000s | 174.484us | 1 | 1 | 100.00 | |
| aes_config_error | 1.000s | 304.862us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| back2back | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| aes_b2b | 2.000s | 122.779us | 1 | 1 | 100.00 | |
| backpressure | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| multi_message | 4 | 4 | 100.00 | |||
| aes_smoke | 1.000s | 174.484us | 1 | 1 | 100.00 | |
| aes_config_error | 1.000s | 304.862us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| aes_alert_reset | 1.000s | 104.582us | 1 | 1 | 100.00 | |
| failure_test | 3 | 3 | 100.00 | |||
| aes_man_cfg_err | 0.000s | 90.157us | 1 | 1 | 100.00 | |
| aes_config_error | 1.000s | 304.862us | 1 | 1 | 100.00 | |
| aes_alert_reset | 1.000s | 104.582us | 1 | 1 | 100.00 | |
| trigger_clear_test | 1 | 1 | 100.00 | |||
| aes_clear | 1.000s | 85.284us | 1 | 1 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 3.000s | 437.345us | 1 | 1 | 100.00 | |
| reset_recovery | 1 | 1 | 100.00 | |||
| aes_alert_reset | 1.000s | 104.582us | 1 | 1 | 100.00 | |
| stress | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| sideload | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 120.016us | 1 | 1 | 100.00 | |
| deinitialization | 1 | 1 | 100.00 | |||
| aes_deinit | 1.000s | 74.535us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aes_stress_all | 6.000s | 314.366us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aes_alert_test | 1.000s | 64.484us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 1.000s | 134.343us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 1.000s | 134.343us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 100.148us | 1 | 1 | 100.00 | |
| aes_csr_rw | 1.000s | 59.306us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 1.000s | 61.423us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 1.000s | 61.851us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 100.148us | 1 | 1 | 100.00 | |
| aes_csr_rw | 1.000s | 59.306us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 1.000s | 61.423us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 1.000s | 61.851us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 1 | 1 | 100.00 | |||
| aes_reseed | 1.000s | 223.412us | 1 | 1 | 100.00 | |
| fault_inject | 2 | 3 | 66.67 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 1.000s | 101.965us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 417.399us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 417.399us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 417.399us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 417.399us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 1.000s | 90.241us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| aes_sec_cm | 2.000s | 1461.145us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 1.000s | 351.601us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aes_tl_intg_err | 1.000s | 351.601us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| aes_alert_reset | 1.000s | 104.582us | 1 | 1 | 100.00 | |
| sec_cm_main_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 417.399us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 417.399us | 1 | 1 | 100.00 | |
| sec_cm_main_config_sparse | 4 | 4 | 100.00 | |||
| aes_smoke | 1.000s | 174.484us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| aes_alert_reset | 1.000s | 104.582us | 1 | 1 | 100.00 | |
| aes_core_fi | 1.000s | 174.500us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_sparse | 3 | 3 | 100.00 | |||
| aes_config_error | 1.000s | 304.862us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| aes_core_fi | 1.000s | 174.500us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 417.399us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_regwen | 2 | 2 | 100.00 | |||
| aes_readability | 1.000s | 55.834us | 1 | 1 | 100.00 | |
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 2 | 2 | 100.00 | |||
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| aes_sideload | 2.000s | 120.016us | 1 | 1 | 100.00 | |
| sec_cm_key_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 55.834us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 55.834us | 1 | 1 | 100.00 | |
| sec_cm_key_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 55.834us | 1 | 1 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 55.834us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 55.834us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_key_sca | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| sec_cm_key_masking | 1 | 1 | 100.00 | |||
| aes_stress | 2.000s | 63.523us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_redun | 3 | 4 | 75.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 1.000s | 101.965us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 78.532us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| sec_cm_cipher_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 1.000s | 101.965us | 1 | 1 | 100.00 | |
| sec_cm_cipher_ctr_redun | 1 | 1 | 100.00 | |||
| aes_cipher_fi | 1.000s | 101.965us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| sec_cm_ctr_fsm_redun | 2 | 3 | 66.67 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 78.532us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_sparse | 3 | 4 | 75.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 1.000s | 101.965us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 78.532us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| aes_alert_reset | 1.000s | 104.582us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 3 | 4 | 75.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 1.000s | 101.965us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 78.532us | 1 | 1 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 3 | 4 | 75.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 1.000s | 101.965us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 78.532us | 1 | 1 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_ctr_fi | 1.000s | 78.532us | 1 | 1 | 100.00 | |
| sec_cm_ghash_fsm_local_esc | 0 | 1 | 0.00 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_local_esc | 2 | 3 | 66.67 | |||
| aes_fi | 2.000s | 161.482us | 0 | 1 | 0.00 | |
| aes_control_fi | 1.000s | 90.852us | 1 | 1 | 100.00 | |
| aes_cipher_fi | 1.000s | 101.965us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| aes_stress_all_with_rand_reset | 4.000s | 379.501us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] | 1 test run | |||
| aes_fi | 88868371386157212899112099217187491312375170371152944704477700387922948657031 | 6462 |
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 4
----| Expected corrupted: 0
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 1 test run | |||
| aes_stress_all_with_rand_reset | 21512385856447646035976353048960321369684101115970697444538479114100273668091 | 429 |
UVM_INFO @ 379501321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|