Simulation Results

Simulation Results: chip

10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
73.19 %

code
75.86 %

assert
96.74 %

func
46.98 %

line
93.78 %

branch
93.35 %

cond
88.65 %

toggle
70.21 %

FSM
33.33 %

Validation stages

V1		94.12%
V2		84.03%
V2S		100.00%
V3		60.00%
unmapped		25.00%

16/17 passed

94.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				3	3	100.00
	chip_sw_example_rom	59.370s	1909.196us	1	1	100.00
	chip_sw_example_manufacturer	153.930s	2629.074us	1	1	100.00
	chip_sw_example_concurrency	134.860s	2667.731us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	396.950s	13505.388us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	446.030s	11197.626us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	515.300s	12500.352us	1	1	100.00
csr_aliasing				0	1	0.00
	chip_csr_aliasing	10800.047s	0.000us	0	1	0.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	606.560s	13662.248us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				1	2	50.00
	chip_csr_aliasing	10800.047s	0.000us	0	1	0.00
	chip_csr_rw	446.030s	11197.626us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	5.190s	235.788us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	286.350s	4026.627us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	286.350s	4026.627us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	286.350s	4026.627us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	358.900s	4603.311us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	358.900s	4603.311us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	337.680s	4175.174us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	395.800s	3981.561us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	388.340s	4010.005us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	932.980s	8305.811us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1029.210s	8660.012us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	576.540s	8467.279us	1	1	100.00

221/263 passed

84.03 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	292.390s	7938.412us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	292.390s	7938.412us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	165.220s	2469.025us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	261.660s	5001.384us	1	1	100.00
chip_sw_sleep_pin_retention				0	1	0.00
	chip_sw_sleep_pin_retention	170.640s	2675.416us	0	1	0.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	346.150s	6881.117us	1	1	100.00
	chip_tap_straps_testunlock0	505.410s	12038.771us	1	1	100.00
	chip_tap_straps_rma	418.070s	8323.521us	1	1	100.00
	chip_tap_straps_prod	82.530s	2252.538us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	325.820s	4832.186us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	325.820s	4832.186us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	523.410s	7209.417us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1254.330s	11665.934us	0	1	0.00
chip_sw_ast_sys_clk_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3583.590s	19487.631us	1	1	100.00
	chip_sw_aes_enc_jitter_en	160.530s	2920.855us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	843.830s	6624.067us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	138.830s	2428.272us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	748.250s	6828.547us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	178.690s	2803.165us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	300.470s	3732.971us	1	1	100.00
	chip_sw_clkmgr_jitter	142.410s	2763.307us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	176.800s	2565.109us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				1	2	50.00
	chip_sw_sensor_ctrl_alert	430.650s	5887.204us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	163.430s	3312.821us	0	1	0.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	158.130s	2744.910us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				0	1	0.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	163.430s	3312.821us	0	1	0.00
chip_sw_smoketest				16	16	100.00
	chip_sw_aes_smoketest	187.160s	2879.683us	1	1	100.00
	chip_sw_aon_timer_smoketest	186.930s	2551.883us	1	1	100.00
	chip_sw_clkmgr_smoketest	130.890s	2610.014us	1	1	100.00
	chip_sw_csrng_smoketest	116.050s	2583.359us	1	1	100.00
	chip_sw_entropy_src_smoketest	656.990s	5157.655us	1	1	100.00
	chip_sw_gpio_smoketest	184.550s	3347.974us	1	1	100.00
	chip_sw_hmac_smoketest	215.510s	3270.174us	1	1	100.00
	chip_sw_kmac_smoketest	167.210s	3151.484us	1	1	100.00
	chip_sw_otbn_smoketest	1226.870s	8711.530us	1	1	100.00
	chip_sw_pwrmgr_smoketest	364.870s	5917.016us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	323.630s	5010.438us	1	1	100.00
	chip_sw_rv_plic_smoketest	139.590s	2840.668us	1	1	100.00
	chip_sw_rv_timer_smoketest	173.340s	2985.451us	1	1	100.00
	chip_sw_rstmgr_smoketest	136.860s	2739.023us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	177.730s	2320.005us	1	1	100.00
	chip_sw_uart_smoketest	147.640s	2296.104us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	177.760s	2922.209us	1	1	100.00
chip_sw_rom_functests				1	1	100.00
	rom_keymgr_dpe_functest	309.450s	4694.073us	1	1	100.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	18257.600s	128027.793us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3086.820s	15352.003us	1	1	100.00
chip_sw_rom_raw_unlock				1	1	100.00
	rom_raw_unlock	310.050s	10851.952us	1	1	100.00
chip_sw_power_idle_load				1	1	100.00
	chip_sw_power_idle_load	347.260s	3851.496us	1	1	100.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	158.470s	3969.575us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				0	1	0.00
	chip_sw_exit_test_unlocked_bootstrap	13200.042s	0.000us	0	1	0.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	2678.910s	60000.000us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	2678.910s	60000.000us	0	1	0.00
tl_d_outstanding_access				3	4	75.00
	chip_csr_aliasing	10800.047s	0.000us	0	1	0.00
	chip_same_csr_outstanding	1154.410s	19139.857us	1	1	100.00
	chip_csr_hw_reset	396.950s	13505.388us	1	1	100.00
	chip_csr_rw	446.030s	11197.626us	1	1	100.00
tl_d_partial_access				3	4	75.00
	chip_csr_aliasing	10800.047s	0.000us	0	1	0.00
	chip_same_csr_outstanding	1154.410s	19139.857us	1	1	100.00
	chip_csr_hw_reset	396.950s	13505.388us	1	1	100.00
	chip_csr_rw	446.030s	11197.626us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	40.630s	1768.333us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	3.020s	43.952us	1	1	100.00
	xbar_smoke_large_delays	29.040s	7381.192us	1	1	100.00
	xbar_smoke_slow_rsp	27.180s	4376.825us	1	1	100.00
	xbar_random_zero_delays	29.000s	555.096us	1	1	100.00
	xbar_random_large_delays	152.800s	37924.419us	1	1	100.00
	xbar_random_slow_rsp	111.190s	18792.225us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	22.140s	905.500us	1	1	100.00
	xbar_error_and_unmapped_addr	8.740s	135.824us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	34.120s	1496.905us	1	1	100.00
	xbar_error_and_unmapped_addr	8.740s	135.824us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	33.630s	1356.384us	1	1	100.00
	xbar_access_same_device_slow_rsp	43.420s	6758.173us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	26.410s	1317.082us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	273.860s	13008.338us	1	1	100.00
	xbar_stress_all_with_error	189.110s	4294.887us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	28.520s	142.716us	1	1	100.00
	xbar_stress_all_with_reset_error	225.850s	7064.186us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3086.820s	15352.003us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2431.430s	42545.262us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3065.320s	15169.340us	1	1	100.00
rom_e2e_boot_policy_valid				14	15	93.33
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2502.550s	11475.340us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	3267.820s	15723.954us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	3175.320s	15832.710us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	3423.070s	15795.594us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	3037.570s	15598.543us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	2511.890s	11855.917us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	3222.260s	15944.332us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	3225.770s	17119.794us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	3247.240s	16011.886us	1	1	100.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	3082.270s	14794.790us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	4596.910s	17321.827us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	53.520s	1783.346us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	5951.490s	24619.774us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	5786.080s	24783.710us	1	1	100.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	5486.650s	23237.486us	1	1	100.00
rom_e2e_sigverify_always				15	15	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	4433.830s	17554.124us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	5653.540s	22618.324us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	6122.100s	31356.897us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	6341.090s	39152.246us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	6104.840s	38835.738us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	3027.950s	33800.974us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	3322.080s	22571.899us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	3196.570s	22918.185us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	3342.180s	18545.790us	1	1	100.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	3181.750s	19128.306us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	2614.720s	19623.928us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	3354.320s	18875.967us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	3874.900s	32123.476us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	3303.910s	22849.742us	1	1	100.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	3121.820s	24563.864us	1	1	100.00
rom_e2e_asm_init				5	5	100.00
	rom_e2e_asm_init_test_unlocked0	2537.670s	11328.578us	1	1	100.00
	rom_e2e_asm_init_dev	3302.450s	16900.026us	1	1	100.00
	rom_e2e_asm_init_prod	3233.940s	15607.150us	1	1	100.00
	rom_e2e_asm_init_prod_end	3212.100s	16290.264us	1	1	100.00
	rom_e2e_asm_init_rma	3240.950s	15110.294us	1	1	100.00
rom_e2e_keymgr_dpe_init				3	3	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_meas	6590.610s	29837.870us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_no_meas	6438.090s	28494.046us	1	1	100.00
	rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas	6755.920s	29085.008us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3501.720s	16765.903us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3349.600s	34700.500us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3349.600s	34700.500us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	183.700s	2499.681us	1	1	100.00
	chip_sw_aes_enc_jitter_en	160.530s	2920.855us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	184.420s	3100.963us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	145.660s	2657.926us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1627.430s	11815.880us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	149.810s	2747.504us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	294.050s	4892.533us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	405.360s	4937.799us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	477.910s	4462.807us	1	1	100.00
	chip_plic_all_irqs_10	315.580s	3986.911us	1	1	100.00
	chip_plic_all_irqs_20	396.060s	4118.568us	1	1	100.00
chip_sw_alert_handler_entropy				0	1	0.00
	chip_sw_alert_handler_entropy	156.060s	3047.320us	0	1	0.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	952.070s	11222.778us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	323.300s	5110.399us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	185.540s	2824.935us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	150.220s	2980.784us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	946.800s	8172.539us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1008.890s	8111.002us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	867.060s	8085.469us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9510.700s	255255.772us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	193.310s	3216.547us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	364.870s	5917.016us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	193.310s	3216.547us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	541.410s	8312.359us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	541.410s	8312.359us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	248.300s	7067.973us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	382.760s	5425.655us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	605.660s	6044.144us	1	1	100.00
	chip_sw_aes_idle	145.660s	2657.926us	1	1	100.00
	chip_sw_hmac_enc_idle	153.690s	2851.784us	1	1	100.00
	chip_sw_kmac_idle	135.580s	2476.388us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	208.600s	4023.179us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	311.590s	4795.357us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	218.540s	4255.019us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	303.260s	4991.713us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	737.060s	8528.720us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	345.370s	4064.700us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	362.460s	4402.647us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	367.400s	4126.409us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	426.910s	4966.774us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	380.140s	3915.355us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	366.950s	4319.693us	1	1	100.00
	chip_sw_ast_clk_outputs	523.410s	7209.417us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1042.570s	19985.517us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	367.400s	4126.409us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	426.910s	4966.774us	1	1	100.00
chip_sw_clkmgr_jitter				8	8	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3583.590s	19487.631us	1	1	100.00
	chip_sw_aes_enc_jitter_en	160.530s	2920.855us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	843.830s	6624.067us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	138.830s	2428.272us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	748.250s	6828.547us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	178.690s	2803.165us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	300.470s	3732.971us	1	1	100.00
	chip_sw_clkmgr_jitter	142.410s	2763.307us	1	1	100.00
chip_sw_clkmgr_extended_range				8	8	100.00
	chip_sw_clkmgr_jitter_reduced_freq	138.840s	2524.891us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4037.330s	25795.491us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	149.760s	2324.836us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	139.070s	2833.206us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1306.580s	11924.203us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	177.900s	3016.963us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	374.420s	5251.921us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	10552.210s	94348.787us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	523.410s	7209.417us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				0	1	0.00
	chip_sw_clkmgr_sleep_frequency	362.280s	4467.971us	0	1	0.00
chip_sw_clkmgr_reset_frequency				0	1	0.00
	chip_sw_clkmgr_reset_frequency	480.220s	7879.721us	0	1	0.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	405.360s	4937.799us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	946.800s	8172.539us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1807.570s	24257.995us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	278.550s	3965.098us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	573.320s	8244.181us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	141.230s	2731.027us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	3876.190s	21933.369us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	123.890s	2566.836us	1	1	100.00
	chip_sw_edn_entropy_reqs	686.270s	5673.473us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	123.890s	2566.836us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1807.570s	24257.995us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	113.530s	2364.398us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	155.300s	2758.515us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	138.830s	2428.272us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	153.690s	2851.784us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1713.890s	12010.180us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1846.230s	12010.320us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	462.650s	5346.326us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	460.980s	4654.036us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	412.130s	4750.170us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	273.090s	3769.197us	1	1	100.00
chip_sw_keymgr_dpe_key_derivation				2	2	100.00
	chip_sw_keymgr_dpe_key_derivation	1268.200s	10344.461us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_jitter_en	748.250s	6828.547us	1	1	100.00
chip_sw_keymgr_dpe_sideload_kmac				1	1	100.00
	chip_sw_keymgr_dpe_sideload_kmac	1088.480s	7990.474us	1	1	100.00
chip_sw_keymgr_dpe_sideload_aes				1	1	100.00
	chip_sw_keymgr_dpe_sideload_aes	1627.430s	11815.880us	1	1	100.00
chip_sw_keymgr_dpe_sideload_otbn				0	1	0.00
	chip_sw_keymgr_dpe_sideload_otbn	3600.045s	0.000us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	173.390s	3315.581us	1	1	100.00
	chip_sw_kmac_mode_kmac	200.530s	2749.091us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	178.690s	2803.165us	1	1	100.00
chip_sw_kmac_app_keymgr_dpe				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1268.200s	10344.461us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	1380.370s	21689.645us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	311.590s	7683.644us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1783.730s	10934.797us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	135.580s	2476.388us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	294.050s	4892.533us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	346.150s	6881.117us	1	1	100.00
	chip_tap_straps_rma	418.070s	8323.521us	1	1	100.00
	chip_tap_straps_prod	82.530s	2252.538us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	147.990s	2826.578us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	1380.370s	21689.645us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	1380.370s	21689.645us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	1380.370s	21689.645us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_dpe_key_derivation_prod	1874.840s	12163.020us	1	1	100.00
chip_sw_lc_ctrl_broadcast				18	21	85.71
	chip_sw_rram_rma_unlocked	228.830s	10010.200us	0	1	0.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	255.230s	3748.948us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	574.390s	6879.559us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	595.360s	6884.225us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	549.360s	6037.404us	0	1	0.00
	chip_sw_lc_ctrl_transition	1380.370s	21689.645us	1	1	100.00
	chip_sw_rram_ctrl_lc_rw_en	317.070s	4275.631us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1268.200s	10344.461us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	638.140s	20942.619us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	397.190s	6794.074us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	1042.570s	19985.517us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	345.370s	4064.700us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	362.460s	4402.647us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	367.400s	4126.409us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	426.910s	4966.774us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	380.140s	3915.355us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	366.950s	4319.693us	1	1	100.00
	chip_tap_straps_dev	346.150s	6881.117us	1	1	100.00
	chip_tap_straps_rma	418.070s	8323.521us	1	1	100.00
	chip_tap_straps_prod	82.530s	2252.538us	1	1	100.00
	chip_rv_dm_lc_disabled	43.150s	3203.299us	0	1	0.00
chip_lc_scrap				3	4	75.00
	chip_sw_lc_ctrl_rma_to_scrap	287.280s	5609.915us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	289.790s	8195.308us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	320.170s	10432.483us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	276.130s	5811.427us	1	1	100.00
chip_lc_test_locked				0	2	0.00
	chip_sw_lc_walkthrough_testunlocks	2596.230s	60000.000us	0	1	0.00
	chip_rv_dm_lc_disabled	43.150s	3203.299us	0	1	0.00
chip_sw_lc_walkthrough				0	5	0.00
	chip_sw_lc_walkthrough_dev	1140.630s	21624.453us	0	1	0.00
	chip_sw_lc_walkthrough_prod	1143.130s	19033.219us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	628.600s	26577.657us	0	1	0.00
	chip_sw_lc_walkthrough_rma	787.210s	15466.679us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	2596.230s	60000.000us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				3	3	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock	144.210s	5175.425us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	166.460s	5660.234us	1	1	100.00
	rom_volatile_raw_unlock	182.530s	5612.899us	1	1	100.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3660.120s	16868.404us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3583.590s	19487.631us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	605.660s	6044.144us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	605.660s	6044.144us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	605.660s	6044.144us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	297.950s	3145.867us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	1380.370s	21689.645us	1	1	100.00
chip_sw_otp_ctrl_keys				3	4	75.00
	chip_sw_otbn_mem_scramble	297.950s	3145.867us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1268.200s	10344.461us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	322.200s	4022.962us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	2682.200s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_entropy				3	4	75.00
	chip_sw_otbn_mem_scramble	297.950s	3145.867us	1	1	100.00
	chip_sw_keymgr_dpe_key_derivation	1268.200s	10344.461us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	322.200s	4022.962us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	2682.200s	60000.000us	0	1	0.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	1380.370s	21689.645us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	331.830s	5484.113us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	147.990s	2826.578us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	5	80.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	255.230s	3748.948us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	574.390s	6879.559us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	595.360s	6884.225us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	549.360s	6037.404us	0	1	0.00
	chip_sw_lc_ctrl_transition	1380.370s	21689.645us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	871.630s	7449.384us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	281.160s	8002.646us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	116.910s	2843.068us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	177.050s	3023.351us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	460.520s	8843.971us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_por_reset	256.580s	4766.212us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	595.260s	19963.473us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				2	2	100.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	887.170s	15287.297us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	541.410s	8312.359us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	228.170s	3533.539us	0	1	0.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	283.070s	3729.492us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	281.160s	8002.646us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	252.780s	3579.983us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	303.890s	8362.491us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	209.880s	5676.961us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	181.810s	3196.497us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	395.350s	6872.111us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	573.640s	5880.076us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	896.220s	9766.580us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1045.270s	19911.056us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	139.900s	2455.907us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	405.360s	4937.799us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	638.140s	20942.619us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	638.140s	20942.619us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	896.220s	9766.580us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	395.350s	6872.111us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	283.070s	3729.492us	1	1	100.00
	chip_sw_pwrmgr_smoketest	364.870s	5917.016us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	194.920s	4111.051us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	353.620s	6104.361us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	269.600s	3501.023us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	952.070s	11222.778us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	195.800s	2865.035us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	405.360s	4937.799us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1008.890s	8111.002us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	518.910s	5174.643us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	530.080s	4634.583us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	156.360s	2969.539us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				0	1	0.00
	chip_sw_rv_core_ibex_icache_invalidate	2682.200s	60000.000us	0	1	0.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	353.620s	6104.361us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	353.620s	6104.361us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	127.130s	2989.849us	1	1	100.00
chip_jtag_csr_rw				0	1	0.00
	chip_jtag_csr_rw	57.140s	2246.462us	0	1	0.00
chip_jtag_mem_access				0	1	0.00
	chip_jtag_mem_access	48.880s	2618.782us	0	1	0.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	194.920s	4111.051us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	181.050s	2701.777us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	183.860s	3254.903us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	418.070s	8323.521us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	43.150s	3203.299us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	477.910s	4462.807us	1	1	100.00
	chip_plic_all_irqs_10	315.580s	3986.911us	1	1	100.00
	chip_plic_all_irqs_20	396.060s	4118.568us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	117.810s	2559.523us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	200.920s	3011.460us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3086.820s	15352.003us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	247.650s	3901.887us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	216.130s	2830.970us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	217.120s	3148.868us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	181.800s	3252.721us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	322.200s	4022.962us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	300.470s	3732.971us	1	1	100.00
chip_sw_sleep_sram_ret_contents				0	2	0.00
	chip_sw_sleep_sram_ret_contents_no_scramble	172.550s	3064.334us	0	1	0.00
	chip_sw_sleep_sram_ret_contents_scramble	143.490s	2522.021us	0	1	0.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	397.190s	6794.074us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	405.360s	4937.799us	1	1	100.00
	chip_sw_data_integrity_escalation	325.820s	4832.186us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	573.640s	5880.076us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	837.910s	20785.030us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	149.790s	2557.987us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	188.200s	3784.507us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	296.330s	3965.829us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	837.910s	20785.030us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	837.910s	20785.030us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2349.230s	20665.202us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2349.230s	20665.202us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	244.230s	5150.277us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3349.600s	34700.500us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	179.470s	2869.631us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	183.650s	2515.952us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	324.850s	3486.433us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	335.090s	3859.541us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	993.050s	8037.505us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5563.080s	31408.135us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2010.740s	12333.860us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	145.450s	3059.446us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	185.270s	2442.773us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	105.080s	2637.864us	1	1	100.00

15/25 passed

60.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	11577.270s	72658.862us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1199.400s	6282.127us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	51.660s	1644.484us	0	1	0.00
	rom_e2e_jtag_debug_dev	57.120s	2227.881us	0	1	0.00
	rom_e2e_jtag_debug_rma	46.220s	1732.280us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	69.420s	2196.199us	0	1	0.00
	rom_e2e_jtag_inject_dev	53.820s	1701.195us	0	1	0.00
	rom_e2e_jtag_inject_rma	60.030s	1849.869us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	33.915s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	274.490s	3519.976us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	332.300s	2699.714us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	1107.710s	5683.640us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	838.190s	6602.576us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	260.160s	2304.538us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	297.390s	3142.610us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	304.410s	5797.005us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	232.140s	3916.996us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	896.220s	9766.580us	1	1	100.00
chip_sw_rom_ctrl_digests				1	1	100.00
	chip_sw_kmac_app_rom	311.590s	7683.644us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	51.660s	1644.484us	0	1	0.00
	rom_e2e_jtag_debug_dev	57.120s	2227.881us	0	1	0.00
	rom_e2e_jtag_debug_rma	46.220s	1732.280us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	355.250s	4524.242us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	405.360s	4937.799us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5732.850s	38414.406us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5732.850s	38414.406us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				0	1	0.00
	chip_sw_spi_device_pinmux_sleep_retention	124.230s	3007.245us	0	1	0.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	358.900s	4603.311us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3066.550s	18645.158us	1	1	100.00

unmapped

2/8 passed

25.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				2	8	25.00
	chip_sw_rstmgr_rst_cnsty_escalation	27.970s	10.380us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	2754.540s	44513.352us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	167.700s	2691.150us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	158.320s	3133.718us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	6.101s	0.000us	0	1	0.00
	ate_bootstrap_flash_erase	522.550s	10010.380us	0	1	0.00
	ate_bootstrap_one_frame	10800.041s	0.000us	0	1	0.00
	ate_bootstrap_disjoint	10800.043s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error				14 test runs
	chip_sw_sleep_pin_retention	12664412670570399148099031333759042389306941087708877125595748525210066713614	379	UVM_INFO @ 2675.415568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_spi_device_pinmux_sleep_retention	7768446081070470090727071319580646043551736564230828008820583531265984778883	374	UVM_INFO @ 3007.244520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	71061445274246022479782815814630926600151140774401498494743551392834925948104	392	UVM_INFO @ 6872.111470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	108223119296250057099393979309025462640663558523060532229700792163206741835616	377	UVM_INFO @ 3533.539144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_por_reset	2853921116409330064898807976152811770518468113854077729188599757987555668806	388	UVM_INFO @ 4766.212081 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_no_scramble	43098118124042270612830636609361072542815454357256470333126422267155010765531	377	UVM_INFO @ 3064.334124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_sleep_sram_ret_contents_scramble	69632705325821709950969249430519378123142377041392967944501644231570034544670	381	UVM_INFO @ 2522.021496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	80376789341600542698799449858443216867928284211550541487403281536907251127223	372	UVM_INFO @ 3312.820616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_sleep_frequency	70257550967029850239754781908945905290208407142497746205263040853228615705684	407	UVM_INFO @ 4467.970944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	74306116533738170347155597217956805180351348887761032271776191150608827106788	374	UVM_INFO @ 3023.351240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_lowpower_cancel	86829715027247065317362045142941706488237677092004943399165005074750854944154	372	UVM_INFO @ 3133.718184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_all_wake_ups	87100617465051803413677372412395980191324932146363111537869450429953901392550	373	UVM_INFO @ 2843.067924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_dm_access_after_wakeup	69820623908682787091946879077896133817480431567520179963400967948358019724960	390	UVM_INFO @ 3254.903008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_power_sleep_load	38979390476461494084547463433664774078370192412661963891277659164902160050	387	UVM_INFO @ 3969.574764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				5 test runs
	chip_csr_aliasing	37223186741849262144863910276337622401069811911800538007900443898404474432565	None
	chip_sw_exit_test_unlocked_bootstrap	97384447096101232716123254418444328343290638606052956440094988692486680938320	None
	chip_sw_keymgr_dpe_sideload_otbn	78888078929027726887509619109582966499043875317816051599910226810363124048278	None
	ate_bootstrap_one_frame	84702519231791405208355774730969779897598629401250432131838867109404358506705	None
	ate_bootstrap_disjoint	35349125776679707169128190814510468462794562304284556865440188751730022613706	None
Error-[NOA] Null object access				4 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	47703883726981495271418767088893286805156536989099760174998017819334698093091	403	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	51670285333932627518561611885824743908236339907451274560238749411067099119212	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	23278357862832228941083253574489264739338027904083848050139719171061097607505	379	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	38861609122842067517842606767935200356230503821835430157391595160187243978246	381	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	39338315644735912552744889010327381960970499044458485439381959800075335665837	433	UVM_INFO @ 21624.453360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	43478383908148150080662809486178449100700969872559224978154828366790672192816	433	UVM_INFO @ 19033.219441 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	94713687262662263851271302979483365220738315195515597880727292077785893559006	405	UVM_INFO @ 15466.678576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue				3 test runs
	chip_sw_lc_walkthrough_testunlocks	111000578937148915542125349993565307670895631164578558371126890888853974481782	487	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_tl_errors	111107288361538605356725699424870543968442579923818877970887456156380459553671	283	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_rv_core_ibex_icache_invalidate	66246177199166086884666556087497502720722956946624542870953126614112537063119	377	UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [] vs [*])				3 test runs
	rom_e2e_jtag_debug_test_unlocked0	26910019297896755717883201852101512631832304171799685014138746831046977884384	359	UVM_INFO @ 1644.483500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_dev	58148479098412115512917863012413402354437623508205478353232476258876299724874	359	UVM_INFO @ 2227.880500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_jtag_debug_rma	25088618565184644471216520986486371784097426095004620817577684546187944198053	359	UVM_INFO @ 1732.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	85240051341199611853543014043936093046775735256876995637361047313203222498034	377	UVM_ERROR @ 3196.497500 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3196.497500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	68446541036520637793846920509421492850508834039283176699760864389784375448088	393	UVM_ERROR @ 8362.490860 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 8362.490860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	chip_sw_alert_handler_lpg_sleep_mode_pings	57160329386490560945131980230102951794864308102997376485631257448520330681578	373	UVM_INFO @ 2980.783908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_alert_handler_entropy	57702238474627695417942539508800200117844174720592414781179001849566445809613	453	UVM_INFO @ 3047.320220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_oneshot	79250463773260837528818508733424999977248913319191172740786808739416492117818	389	UVM_INFO @ 12010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	6104261028485382541090362099175982518160534113574893333507615873316929947268	401	UVM_INFO @ 12010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!				2 test runs
	chip_jtag_csr_rw	49594827718571664647918953858227210993465330124519588629653254085192521927701	5365	UVM_INFO @ 2246.461902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_jtag_mem_access	8640363475349456272938639601574786686281727270719624015935163609158146533695	5365	UVM_INFO @ 2618.781837 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				2 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	68148775063317266917953317397549744142533130285555570085368094513380186435391	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	275948639550034722582912228723266013955534003040180778976610751396492040481	None	---- STDERR ---- Another command (pid=521957) is running. Waiting for it to complete on the server (server_pid=182137)... Another command (pid=569179) is running. Waiting for it to complete on the server (server_pid=182137)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	75459732645417227502241071096389428545034488164225755737979907702282470544932	365	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	111646250682540675857870895654201811276394403991602375509113484581536032038845	391	UVM_INFO @ 2830.969737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!				1 test run
	chip_sw_rram_rma_unlocked	11158806482354409736529855829897251752288986004524311734129441850873440611098	337	UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	114466373546123947878654516103618883150124275100900336767982091408671214364519	404	UVM_INFO @ 6037.403750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:715)] CHECK-fail: Alert handler NMI state not expected:				1 test run
	chip_sw_otp_ctrl_escalation	31289569904750068722552758226174035353107325652337792796202383121282493920961	379	alert_enable:1 alert_raised:0 UVM_INFO @ 3142.610371 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl				1 test run
	chip_sw_lc_ctrl_test_locked0_to_scrap	91749788749745283219324959768434058458129721431034872620585201722544501929765	375	UVM_INFO @ 10432.483331 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_walkthrough_prodend	102393361776581173869071968148736763231128664740962849435541284873523267594892	372	UVM_INFO @ 26577.656964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	40187733786402263238068658881359012361942188335246126377209426612305103502397	396	UVM_INFO @ 34700.499504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:385)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	89590738638189246474033193993674208178474500672905122589891289927731941681960	371	UVM_INFO @ 2747.503855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	89251077733017713309792581200023127182656555058698052824233709837767161523024	373	UVM_INFO @ 2824.934900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.				1 test run
	chip_sw_clkmgr_reset_frequency	39937097498431983533144772643278267910759661434235602318891156639632940261443	400	UVM_INFO @ 7879.720884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	63525684695639912918887333628998064267531586315151251013411074311561355310978	407	UVM_INFO @ 3519.975710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	68557934692465613537939915157733208940034073749869528224485538420763035561160	299	UVM_INFO @ 3203.298741 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	67426310525473977694251346066688981184559523116029377365620387441147535063861	391	UVM_INFO @ 11665.933834 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	37106821614357462876434544717983716458250744351609381079910446438874220201381	339	UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'				1 test run
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	90487779508992809374392362719046058012148499253955425898539641052598490756575	418	UVM_ERROR @ 1783.345908 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M UVM_INFO @ 1783.345908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---