Simulation Results: clkmgr

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 92.99 %
  • code
  • 98.47 %
  • assert
  • 94.21 %
  • func
  • 86.28 %
  • line
  • 99.14 %
  • branch
  • 98.96 %
  • cond
  • 94.56 %
  • toggle
  • 99.68 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.880s 84.607us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.730s 32.038us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.710s 41.751us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.990s 284.896us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.720s 14.843us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.790s 32.119us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.710s 41.751us 1 1 100.00
clkmgr_csr_aliasing 0.720s 14.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.630s 43.523us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.640s 27.482us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.250s 260.758us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.670s 16.879us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.880s 84.607us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.390s 331.138us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.310s 2417.144us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.390s 331.138us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 27.170s 12867.726us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.690s 17.827us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.760s 270.852us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.760s 270.852us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 32.038us 1 1 100.00
clkmgr_csr_rw 0.710s 41.751us 1 1 100.00
clkmgr_csr_aliasing 0.720s 14.843us 1 1 100.00
clkmgr_same_csr_outstanding 1.150s 257.572us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 32.038us 1 1 100.00
clkmgr_csr_rw 0.710s 41.751us 1 1 100.00
clkmgr_csr_aliasing 0.720s 14.843us 1 1 100.00
clkmgr_same_csr_outstanding 1.150s 257.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
clkmgr_sec_cm 1.980s 318.104us 1 1 100.00
clkmgr_tl_intg_err 1.790s 137.771us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.580s 200.808us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.580s 200.808us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.580s 200.808us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.580s 200.808us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.230s 186.388us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.790s 137.771us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.390s 331.138us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.310s 2417.144us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.580s 200.808us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.750s 45.544us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.690s 86.797us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.580s 22.354us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.830s 64.622us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.040s 195.525us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.710s 41.751us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 1.980s 318.104us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 41.751us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 41.751us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 1.980s 318.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.930s 1353.591us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 28.380s 3213.120us 1 1 100.00