Simulation Results: edn/edn0

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.94 %
  • code
  • 81.16 %
  • assert
  • 96.31 %
  • func
  • 80.36 %
  • line
  • 97.72 %
  • branch
  • 91.35 %
  • cond
  • 85.61 %
  • toggle
  • 75.73 %
  • FSM
  • 55.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.630s 71.782us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.720s 34.229us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 40.560us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.610s 48.881us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.710s 75.479us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.940s 78.183us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 40.560us 1 1 100.00
edn_csr_aliasing 0.710s 75.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.950s 47.526us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.950s 47.526us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.950s 47.526us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.840s 23.294us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.910s 59.670us 1 1 100.00
errs 1 1 100.00
edn_err 0.840s 28.498us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 12.253us 1 1 100.00
edn_disable_auto_req_mode 0.920s 463.543us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.830s 44.144us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.650s 38.572us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.670s 29.521us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.950s 83.849us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.950s 83.849us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.720s 34.229us 1 1 100.00
edn_csr_rw 0.780s 40.560us 1 1 100.00
edn_csr_aliasing 0.710s 75.479us 1 1 100.00
edn_same_csr_outstanding 0.860s 22.919us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.720s 34.229us 1 1 100.00
edn_csr_rw 0.780s 40.560us 1 1 100.00
edn_csr_aliasing 0.710s 75.479us 1 1 100.00
edn_same_csr_outstanding 0.860s 22.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.840s 1062.080us 1 1 100.00
edn_tl_intg_err 2.320s 198.875us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.760s 16.707us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.910s 59.670us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.840s 1062.080us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.840s 1062.080us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.840s 1062.080us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.840s 1062.080us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.910s 59.670us 1 1 100.00
edn_sec_cm 2.840s 1062.080us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.910s 59.670us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.320s 198.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 28.330s 1982.446us 1 1 100.00