Simulation Results: edn/edn1

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.31 %
  • code
  • 83.71 %
  • assert
  • 98.18 %
  • func
  • 80.04 %
  • line
  • 98.18 %
  • branch
  • 92.86 %
  • cond
  • 89.08 %
  • toggle
  • 93.00 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.640s 29.876us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.660s 16.380us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.700s 44.956us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.740s 560.439us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.760s 17.033us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.760s 64.258us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.700s 44.956us 1 1 100.00
edn_csr_aliasing 0.760s 17.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.730s 53.937us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.730s 53.937us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.730s 53.937us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 21.693us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.840s 294.929us 1 1 100.00
errs 1 1 100.00
edn_err 0.630s 34.027us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 12.096us 1 1 100.00
edn_disable_auto_req_mode 0.890s 257.445us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.600s 2680.092us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.690s 44.377us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 73.371us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.080s 1311.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.080s 1311.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.660s 16.380us 1 1 100.00
edn_csr_rw 0.700s 44.956us 1 1 100.00
edn_csr_aliasing 0.760s 17.033us 1 1 100.00
edn_same_csr_outstanding 0.830s 60.136us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.660s 16.380us 1 1 100.00
edn_csr_rw 0.700s 44.956us 1 1 100.00
edn_csr_aliasing 0.760s 17.033us 1 1 100.00
edn_same_csr_outstanding 0.830s 60.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 1.930s 2154.676us 1 1 100.00
edn_tl_intg_err 1.080s 486.862us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.600s 33.005us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.840s 294.929us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.930s 2154.676us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 1.930s 2154.676us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 1.930s 2154.676us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 1.930s 2154.676us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.840s 294.929us 1 1 100.00
edn_sec_cm 1.930s 2154.676us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.840s 294.929us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.080s 486.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 57.970s 6322.568us 1 1 100.00