Simulation Results: hmac

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.91 %
  • code
  • 86.45 %
  • assert
  • 97.16 %
  • func
  • 44.12 %
  • line
  • 99.59 %
  • branch
  • 99.19 %
  • cond
  • 96.14 %
  • toggle
  • 46.17 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.310s 328.772us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.570s 29.860us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.520s 16.591us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 3.470s 163.090us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 0.690s 36.048us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 425.710s 56482.830us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.520s 16.591us 1 1 100.00
hmac_csr_aliasing 0.690s 36.048us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 4.620s 6163.915us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 77.200s 13126.126us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.900s 953.871us 1 1 100.00
hmac_test_sha384_vectors 372.480s 98753.217us 1 1 100.00
hmac_test_sha512_vectors 320.120s 16151.076us 1 1 100.00
hmac_test_hmac256_vectors 9.180s 1211.808us 1 1 100.00
hmac_test_hmac384_vectors 6.410s 633.219us 1 1 100.00
hmac_test_hmac512_vectors 9.580s 1727.113us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.220s 2074.576us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 443.540s 24278.007us 1 1 100.00
error 1 1 100.00
hmac_error 70.270s 30278.183us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 95.110s 3958.369us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.310s 328.772us 1 1 100.00
hmac_long_msg 4.620s 6163.915us 1 1 100.00
hmac_back_pressure 77.200s 13126.126us 1 1 100.00
hmac_datapath_stress 443.540s 24278.007us 1 1 100.00
hmac_burst_wr 12.220s 2074.576us 1 1 100.00
hmac_stress_all 2731.170s 147269.535us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.310s 328.772us 1 1 100.00
hmac_long_msg 4.620s 6163.915us 1 1 100.00
hmac_back_pressure 77.200s 13126.126us 1 1 100.00
hmac_datapath_stress 443.540s 24278.007us 1 1 100.00
hmac_wipe_secret 95.110s 3958.369us 1 1 100.00
hmac_test_sha256_vectors 7.900s 953.871us 1 1 100.00
hmac_test_sha384_vectors 372.480s 98753.217us 1 1 100.00
hmac_test_sha512_vectors 320.120s 16151.076us 1 1 100.00
hmac_test_hmac256_vectors 9.180s 1211.808us 1 1 100.00
hmac_test_hmac384_vectors 6.410s 633.219us 1 1 100.00
hmac_test_hmac512_vectors 9.580s 1727.113us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.310s 328.772us 1 1 100.00
hmac_long_msg 4.620s 6163.915us 1 1 100.00
hmac_back_pressure 77.200s 13126.126us 1 1 100.00
hmac_datapath_stress 443.540s 24278.007us 1 1 100.00
hmac_burst_wr 12.220s 2074.576us 1 1 100.00
hmac_error 70.270s 30278.183us 1 1 100.00
hmac_wipe_secret 95.110s 3958.369us 1 1 100.00
hmac_test_sha256_vectors 7.900s 953.871us 1 1 100.00
hmac_test_sha384_vectors 372.480s 98753.217us 1 1 100.00
hmac_test_sha512_vectors 320.120s 16151.076us 1 1 100.00
hmac_test_hmac256_vectors 9.180s 1211.808us 1 1 100.00
hmac_test_hmac384_vectors 6.410s 633.219us 1 1 100.00
hmac_test_hmac512_vectors 9.580s 1727.113us 1 1 100.00
hmac_stress_all 2731.170s 147269.535us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 2731.170s 147269.535us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.510s 14.657us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.560s 48.279us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.100s 230.435us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.100s 230.435us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.570s 29.860us 1 1 100.00
hmac_csr_rw 0.520s 16.591us 1 1 100.00
hmac_csr_aliasing 0.690s 36.048us 1 1 100.00
hmac_same_csr_outstanding 1.380s 49.563us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.570s 29.860us 1 1 100.00
hmac_csr_rw 0.520s 16.591us 1 1 100.00
hmac_csr_aliasing 0.690s 36.048us 1 1 100.00
hmac_same_csr_outstanding 1.380s 49.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.640s 356.255us 1 1 100.00
hmac_tl_intg_err 2.150s 183.740us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.150s 183.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.310s 328.772us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.450s 362.707us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 69.230s 4637.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.090s 27.268us 1 1 100.00