Simulation Results

Simulation Results: i2c

10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
85.99 %

code
78.38 %

assert
97.04 %

func
82.56 %

line
96.38 %

branch
92.33 %

cond
85.12 %

toggle
74.04 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	46.780s	8388.381us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	5.040s	1319.384us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.560s	19.942us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.630s	76.337us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	1.930s	347.126us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	0.520s	22.742us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.650s	72.650us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.630s	76.337us	1	1	100.00
	i2c_csr_aliasing	0.520s	22.742us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.560s	5.901us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	55.930s	7977.796us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	35.780s	3138.652us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.570s	45.696us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	84.520s	12106.785us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	25.580s	1942.141us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.770s	74.981us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.990s	727.942us	1	1	100.00
	i2c_host_fifo_reset_rx	5.540s	895.642us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	39.190s	9352.266us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	22.610s	716.408us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.310s	569.916us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.190s	1793.210us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	92.900s	27148.976us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.320s	12569.820us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	12.270s	587.211us	1	1	100.00
	i2c_target_intr_smoke	2.840s	2588.909us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.120s	245.871us	1	1	100.00
	i2c_target_fifo_reset_tx	1.080s	1557.008us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	130.520s	34612.392us	1	1	100.00
	i2c_target_stress_rd	12.270s	587.211us	1	1	100.00
	i2c_target_intr_stress_wr	3.360s	9090.716us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.170s	3910.266us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2.060s	409.087us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.530s	2740.851us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	16.060s	10186.587us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.430s	950.429us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.890s	518.267us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	35.780s	3138.652us	1	1	100.00
	i2c_host_perf_precise	11.370s	1932.945us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	22.610s	716.408us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.590s	82.819us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.770s	1589.817us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.300s	2255.138us	1	1	100.00
	i2c_target_nack_txstretch	1.230s	594.642us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	9.900s	1064.530us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.420s	1937.805us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.560s	20.816us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.580s	42.995us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.530s	175.022us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.530s	175.022us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.560s	19.942us	1	1	100.00
	i2c_csr_rw	0.630s	76.337us	1	1	100.00
	i2c_csr_aliasing	0.520s	22.742us	1	1	100.00
	i2c_same_csr_outstanding	1.090s	62.094us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.560s	19.942us	1	1	100.00
	i2c_csr_rw	0.630s	76.337us	1	1	100.00
	i2c_csr_aliasing	0.520s	22.742us	1	1	100.00
	i2c_same_csr_outstanding	1.090s	62.094us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.280s	145.481us	1	1	100.00
	i2c_sec_cm	0.680s	45.480us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.280s	145.481us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	11.720s	4637.245us	1
target_error_intr				1
	i2c_target_unexp_stop	0.840s	88.165us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	2.450s	290.912us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	24059051738741885809529264739983450539495754330517862915457241666889704503359	94	UVM_INFO @ 5901380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	68406765803887286725350703549426753515008529046632586306950576319916472279470	109	UVM_INFO @ 7977796421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	53491627107691462679613592677696130867096097535800468325464495920595554692505	100	UVM_INFO @ 4637244746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	42207363214331749947705159438190604692223763364220073180194396165582551715627	90	UVM_INFO @ 290911937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	14033831263474383096630934084953030102003407411177407558927141059381293650120	90	UVM_INFO @ 1793209918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	7459066081200230533732994851805530137647851435949935179469432821971633534916	84	UVM_INFO @ 88165308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	51222325353246267595437113882832531825169123955165540160464523962772017557211	85	UVM_INFO @ 10186587047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	108042430508570078279013789735599929947150201908692819177236012454441409797274	91	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @47873