Simulation Results: keymgr_dpe/earlgrey

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.09 %
  • code
  • 82.44 %
  • assert
  • 97.67 %
  • func
  • 15.15 %
  • line
  • 97.19 %
  • branch
  • 93.77 %
  • cond
  • 86.34 %
  • toggle
  • 59.23 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 7.850s 1592.328us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 0.700s 144.362us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.740s 17.190us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 4.140s 3669.118us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.120s 177.905us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 0.740s 65.374us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 0.740s 17.190us 1 1 100.00
keymgr_dpe_csr_aliasing 1.120s 177.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.630s 36.166us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 0.610s 77.585us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 0.960s 17.480us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 0.960s 17.480us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.700s 144.362us 1 1 100.00
keymgr_dpe_csr_rw 0.740s 17.190us 1 1 100.00
keymgr_dpe_csr_aliasing 1.120s 177.905us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.680s 138.660us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.700s 144.362us 1 1 100.00
keymgr_dpe_csr_rw 0.740s 17.190us 1 1 100.00
keymgr_dpe_csr_aliasing 1.120s 177.905us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.680s 138.660us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 6.870s 604.642us 1 1 100.00
keymgr_dpe_tl_intg_err 2.160s 477.777us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.070s 40.345us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.070s 40.345us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.070s 40.345us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.070s 40.345us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 1.120s 120.004us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 6.870s 604.642us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 6.870s 604.642us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 2 test runs
keymgr_dpe_shadow_reg_errors 106484085362064855364119211798441987894800644039584945121967030478323346416101 83
UVM_ERROR @ 40344650 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 40344650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_shadow_reg_errors_with_csr_rw 104397640356043621788558633526973236021187202212382903881251747486540087207216 83
UVM_ERROR @ 120004428 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 120004428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---