Simulation Results: lc_ctrl/volatile_unlock_disabled

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.47 %
  • code
  • 83.35 %
  • assert
  • 94.69 %
  • func
  • 93.37 %
  • line
  • 97.15 %
  • branch
  • 93.47 %
  • cond
  • 79.31 %
  • toggle
  • 83.27 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.540s 37.653us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.510s 26.107us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.510s 19.088us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.880s 180.036us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.590s 24.690us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.610s 177.855us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.510s 19.088us 1 1 100.00
lc_ctrl_csr_aliasing 0.590s 24.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.820s 145.487us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.530s 373.330us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.480s 52.316us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 0.980s 481.579us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.230s 704.509us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_prog_failure 0.980s 481.579us 1 1 100.00
lc_ctrl_errors 3.230s 704.509us 1 1 100.00
lc_ctrl_security_escalation 2.270s 218.382us 1 1 100.00
lc_ctrl_jtag_state_failure 18.000s 5505.183us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.730s 345.120us 1 1 100.00
lc_ctrl_jtag_errors 11.530s 6969.667us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 0.990s 205.850us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.130s 442.893us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.730s 345.120us 1 1 100.00
lc_ctrl_jtag_errors 11.530s 6969.667us 1 1 100.00
lc_ctrl_jtag_access 2.560s 1355.580us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.550s 966.122us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.040s 1118.211us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.800s 62.431us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.620s 1592.805us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 0.890s 614.932us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.540s 29.890us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.250s 149.503us 1 1 100.00
lc_ctrl_jtag_alert_test 0.510s 20.966us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 19.560s 9371.187us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.530s 17.843us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 8.800s 786.824us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.560s 48.491us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.080s 246.344us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.080s 246.344us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.510s 26.107us 1 1 100.00
lc_ctrl_csr_rw 0.510s 19.088us 1 1 100.00
lc_ctrl_csr_aliasing 0.590s 24.690us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.760s 159.226us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.510s 26.107us 1 1 100.00
lc_ctrl_csr_rw 0.510s 19.088us 1 1 100.00
lc_ctrl_csr_aliasing 0.590s 24.690us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.760s 159.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
lc_ctrl_tl_intg_err 0.850s 256.806us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 0.850s 256.806us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.530s 373.330us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.630s 523.987us 1 1 100.00
lc_ctrl_sec_cm 3.810s 149.529us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 2.270s 218.382us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.820s 145.487us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.130s 442.893us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.190s 668.378us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.190s 668.378us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 2.510s 208.437us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.430s 431.191us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.430s 431.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 17.390s 1971.520us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_stress_all 39217494415119335490836365919940583541104294036554378767757876900594982646174 1848
UVM_INFO @ 786823631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---