Simulation Results: lc_ctrl/volatile_unlock_enabled

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.12 %
  • code
  • 83.33 %
  • assert
  • 94.55 %
  • func
  • 92.47 %
  • line
  • 97.17 %
  • branch
  • 93.57 %
  • cond
  • 79.22 %
  • toggle
  • 84.99 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.770s 98.595us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.540s 217.242us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.530s 39.242us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.840s 111.744us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.590s 28.242us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.990s 30.380us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.530s 39.242us 1 1 100.00
lc_ctrl_csr_aliasing 0.590s 28.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.460s 66.315us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 2.980s 1364.615us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.550s 13.837us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.880s 283.930us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.960s 823.271us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_prog_failure 1.880s 283.930us 1 1 100.00
lc_ctrl_errors 3.960s 823.271us 1 1 100.00
lc_ctrl_security_escalation 2.200s 190.957us 1 1 100.00
lc_ctrl_jtag_state_failure 9.990s 1087.115us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.810s 367.011us 1 1 100.00
lc_ctrl_jtag_errors 14.760s 4234.652us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 0.900s 428.936us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.900s 544.220us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.810s 367.011us 1 1 100.00
lc_ctrl_jtag_errors 14.760s 4234.652us 1 1 100.00
lc_ctrl_jtag_access 1.750s 266.565us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.280s 4081.254us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.150s 2085.325us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.740s 243.403us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 2.430s 409.955us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 0.870s 174.911us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.750s 44.034us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 0.980s 85.349us 1 1 100.00
lc_ctrl_jtag_alert_test 0.930s 127.900us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.500s 690.745us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.510s 24.934us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 53.040s 19091.002us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.630s 17.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 0.910s 184.042us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 0.910s 184.042us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.540s 217.242us 1 1 100.00
lc_ctrl_csr_rw 0.530s 39.242us 1 1 100.00
lc_ctrl_csr_aliasing 0.590s 28.242us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.810s 49.425us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.540s 217.242us 1 1 100.00
lc_ctrl_csr_rw 0.530s 39.242us 1 1 100.00
lc_ctrl_csr_aliasing 0.590s 28.242us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.810s 49.425us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
lc_ctrl_tl_intg_err 0.690s 779.108us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 0.690s 779.108us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 2.980s 1364.615us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.900s 247.980us 1 1 100.00
lc_ctrl_sec_cm 3.530s 599.766us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 2.200s 190.957us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.460s 66.315us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.900s 544.220us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.260s 1384.864us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.260s 1384.864us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 2.770s 2412.941us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.540s 340.387us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 2.540s 340.387us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 5.590s 1556.047us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_stress_all_with_rand_reset 35252326126706236587060812144956684390906597925635633207002365459341568046968 1037
UVM_INFO @ 1556046637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---