Simulation Results: otbn

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.10 %
  • code
  • 86.08 %
  • assert
  • 89.76 %
  • func
  • 97.46 %
  • block
  • 99.22 %
  • line
  • 99.42 %
  • branch
  • 94.38 %
  • toggle
  • 84.31 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
76.47%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 13.000s 741.310us 1 1 100.00
otbn_smoke_vectorized 8.000s 28.786us 1 1 100.00
single_binary 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 36.634us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 12.943us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 328.665us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 27.330us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 40.477us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 12.943us 1 1 100.00
otbn_csr_aliasing 3.000s 27.330us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 67.000s 1533.957us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 24.000s 633.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 29.000s 115.352us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 26.000s 181.709us 0 1 0.00
wfi 0 3 0.00
otbn_wfi_smoke 5.000s 6.895us 0 1 0.00
otbn_wfi_sec_wipe 4.000s 10.469us 0 1 0.00
otbn_wfi_back_to_back 5.000s 12.051us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 22.000s 62.991us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 42.000s 255.145us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 7.000s 59.514us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 9.000s 40.854us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 13.758us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 23.021us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 17.711us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 72.853us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 72.853us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 36.634us 1 1 100.00
otbn_csr_rw 3.000s 12.943us 1 1 100.00
otbn_csr_aliasing 3.000s 27.330us 1 1 100.00
otbn_same_csr_outstanding 5.000s 93.373us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 36.634us 1 1 100.00
otbn_csr_rw 3.000s 12.943us 1 1 100.00
otbn_csr_aliasing 3.000s 27.330us 1 1 100.00
otbn_same_csr_outstanding 5.000s 93.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 32.237us 1 1 100.00
otbn_dmem_err 9.000s 19.575us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 175.054us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 234.185us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 61.400us 1 1 100.00
otbn_urnd_err 4.000s 21.879us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 29.465us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 12.000s 116.047us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 278.995us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
otbn_tl_intg_err 16.000s 2625.974us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 35.000s 686.010us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 741.310us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 19.575us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 32.237us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 2625.974us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 59.514us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 32.237us 1 1 100.00
otbn_dmem_err 9.000s 19.575us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 40.854us 1 1 100.00
otbn_illegal_mem_acc 4.000s 29.465us 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 32.237us 1 1 100.00
otbn_dmem_err 9.000s 19.575us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 40.854us 1 1 100.00
otbn_illegal_mem_acc 4.000s 29.465us 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 59.514us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 9.000s 32.237us 1 1 100.00
otbn_dmem_err 9.000s 19.575us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 40.854us 1 1 100.00
otbn_illegal_mem_acc 4.000s 29.465us 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 99.136us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 48.053us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 19.000s 93.141us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 19.000s 93.141us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 33.332us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 199.749us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 42.327us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 42.327us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 59.062us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 22.000s 62.991us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 20.000s 85.933us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 5.000s 15.817us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 3548.405us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 1.816s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. 2 test runs
otbn_wfi_smoke 105342391181629275324484721139265341233105809936991162936105836169402932319972 118
UVM_INFO @ 6895128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_back_to_back 73275734411598670543763089459764010211487638280758321608224842383642677650503 111
UVM_INFO @ 12051378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 55824989565555820594664063624648100341895030438449481255313078376294200848088 284
UVM_INFO @ 181709184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_stress_all_with_rand_reset 43873147345764341637841528077459647915520623616484765282890471088190332434245 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 94291620026098394365194564909281530547299994613986717925965190285435483154613 111
UVM_ERROR @ 21879176 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 21879176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value. 1 test run
otbn_wfi_sec_wipe 66861059092402605183749876835501848758058251407703411721083879323170524257766 116
UVM_FATAL @ 10468621 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 10468621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---