Simulation Results: otp_ctrl

 
10/09/2026 17:06:13 DVSim: v1.52.2 sha: 5bf9391 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 76.48 %
  • code
  • 72.86 %
  • assert
  • 92.53 %
  • func
  • 64.06 %
  • line
  • 87.58 %
  • branch
  • 80.50 %
  • cond
  • 88.18 %
  • toggle
  • 70.01 %
  • FSM
  • 38.02 %
Validation stages
V1
100.00%
V2
65.00%
V2S
55.56%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 0.900s 206.372us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 1.620s 275.422us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 0.910s 162.510us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 0.790s 45.370us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.060s 826.828us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 0.870s 50.406us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.110s 146.836us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 0.790s 45.370us 1 1 100.00
otp_ctrl_csr_aliasing 0.870s 50.406us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 0.890s 523.609us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 0.690s 40.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 9.940s 814.364us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.040s 133.354us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 5.350s 4639.856us 0 1 0.00
otp_ctrl_check_fail 10.960s 13350.144us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.080s 144.253us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 18.190s 25200.722us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 2.660s 1230.929us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 7.380s 824.483us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 9.200s 2563.198us 0 1 0.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 3.730s 682.645us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 5.720s 774.734us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 6.720s 706.989us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 0.730s 147.010us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 0.910s 62.866us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.280s 108.519us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.280s 108.519us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 0.910s 162.510us 1 1 100.00
otp_ctrl_csr_rw 0.790s 45.370us 1 1 100.00
otp_ctrl_csr_aliasing 0.870s 50.406us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.180s 132.653us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 0.910s 162.510us 1 1 100.00
otp_ctrl_csr_rw 0.790s 45.370us 1 1 100.00
otp_ctrl_csr_aliasing 0.870s 50.406us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.180s 132.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
otp_ctrl_tl_intg_err 8.580s 5162.329us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 8.580s 5162.329us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 1.620s 275.422us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 1.620s 275.422us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_dai_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
sec_cm_part_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
otp_ctrl_macro_errs 3.730s 682.645us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
sec_cm_timer_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_dai_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
sec_cm_part_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
otp_ctrl_macro_errs 3.730s 682.645us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
sec_cm_timer_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 3.100s 1943.280us 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.040s 133.354us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 10.960s 13350.144us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 18.190s 25200.722us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 18.190s 25200.722us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 18.190s 25200.722us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 18.190s 25200.722us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 18.190s 25200.722us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 1.620s 275.422us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 18.190s 25200.722us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 1.620s 275.422us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 17.540s 2652.511us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.080s 144.253us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 1.620s 275.422us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 1.620s 275.422us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 3.730s 682.645us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 7.210s 3517.025us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 46.010s 3328.300us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 2 test runs
otp_ctrl_parallel_lc_esc 25528848372141859581179894751857006928548769017416094769973755483732439413322 1405
UVM_INFO @ 1943280475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15669186683732307711466622611336454110865645155290870559600110378238417264764 14875
UVM_INFO @ 3328300367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error 2 test runs
otp_ctrl_dai_errs 49710742607236672693497989840552553613879685891442661221220826601146342591894 10912
UVM_INFO @ 2563198056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 79417286945919068352237165449869250056851653157504518023169139305137249708818 5168
UVM_INFO @ 706988960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 111554271910305204188079221780522293692423101252948999694086329241393620932995 9892
UVM_INFO @ 13350143878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 114206249532151597598739142181644165733595833528002924369399390067378743510272 3428
UVM_INFO @ 682645332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 1 test run
otp_ctrl_background_chks 36460708157107755328296973038134064964830492680697252095766928742071977131272 3009
UVM_INFO @ 4639856194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 1 test run
otp_ctrl_parallel_key_req 34201318031343450713273682714898677499222443012453887942505254748950695612207 2975
UVM_INFO @ 1230928607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [otp_ctrl_common_vseq] Expected alert (fatal_check_error) did not fire in * cycles. 1 test run
otp_ctrl_sec_cm 59445761187218101930058086509681261923791012126822713150162170700700071537201 737
UVM_INFO @ 2652510805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---